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/linux/tools/testing/selftests/bpf/prog_tests/
H A Dtracing_struct.c97 ASSERT_EQ(skel->bss->t9_a, 16, "t9:a"); in test_struct_many_args()
98 ASSERT_EQ(skel->bss->t9_b, 17, "t9:b"); in test_struct_many_args()
99 ASSERT_EQ(skel->bss->t9_c, 18, "t9:c"); in test_struct_many_args()
100 ASSERT_EQ(skel->bss->t9_d, 19, "t9:d"); in test_struct_many_args()
101 ASSERT_EQ(skel->bss->t9_e, 20, "t9:e"); in test_struct_many_args()
102 ASSERT_EQ(skel->bss->t9_f, 21, "t9:f"); in test_struct_many_args()
103 ASSERT_EQ(skel->bss->t9_g, 22, "t9:f"); in test_struct_many_args()
104 ASSERT_EQ(skel->bss->t9_h_a, 23, "t9:h.a"); in test_struct_many_args()
105 ASSERT_EQ(skel->bss->t9_h_b, 24, "t9:h.b"); in test_struct_many_args()
106 ASSERT_EQ(skel->bss->t9_h_c, 25, "t9:h.c"); in test_struct_many_args()
[all …]
/linux/arch/mips/kernel/
H A Dcps-vec-ns16550.S34 * @t9: UART base address
37 1: UART_L t0, UART_LSR_OFS(t9)
40 UART_S a0, UART_TX_OFS(t9)
47 * @t9: UART base address
67 * @t9: UART base address
84 * @t9: UART base address
101 * @t9: UART base address
118 * @t9: UART base address
137 * @t9: UART base address
176 li t9, CKSEG1ADDR(CONFIG_MIPS_CPS_NS16550_BASE)
H A Dcps-vec.S143 move a1, t9
270 * struct vpe_boot_config in v1, VPE ID in t9
282 li t9, 0
291 mfc0 t9, CP0_GLOBALNUMBER
292 andi t9, t9, MIPS_GLOBALNUMBER_VP
311 mfc0 t9, $15, 1
312 and t9, t9, t1
317 mul v1, t9, t1
H A Docteon_switch.S48 LONG_L t9, LONGSIZE(t1)/* Load from CVMSEG */
53 LONG_S t9, -LONGSIZE(t2)/* Store CVMSEG to thread storage */
65 LONG_L t9, TASK_STACK_CANARY(a1)
66 LONG_S t9, 0(t8)
99 dmfc0 t9, $9,7 /* CvmCtl register. */
108 bbit1 t9, 28, 1f
116 1: bbit1 t9, 26, 3f /* done if CvmCtl[NOCRYPTO] set */
262 dmfc0 t9, $9,7 /* CvmCtl register. */
273 bbit1 t9, 28, 2f /* Skip LLM if CvmCtl[NODFA_CP2] is set */
283 bbit1 t9, 26, done_restore /* done if CvmCtl[NOCRYPTO] set */
H A Dr4k_switch.S36 LONG_L t9, TASK_STACK_CANARY(a1)
37 LONG_S t9, 0(t8)
H A Dr2300_switch.S40 LONG_L t9, TASK_STACK_CANARY(a1)
41 LONG_S t9, 0(t8)
/linux/arch/mips/boot/compressed/
H A Dhead.S35 PTR_LA t9, decompress_kernel
36 jalr t9
43 PTR_LI t9, KERNEL_ENTRY
44 jalr t9
/linux/arch/mips/include/asm/mach-loongson64/
H A Dkernel-entry-init.h81 /* a0:base t1:cpuid t2:node t9:count */
93 2: li t9, 0x100 /* wait for init loop */
94 3: addiu t9, -1 /* limit mailbox access */
95 bnez t9, 3b
/linux/tools/perf/util/hisi-ptt-decoder/
H A Dhisi-ptt-pkt-decoder.c36 * DW0 [ Fmt ][ Type ][T9][T8][TH][SO][ Length ][ Time ]
80 uint32_t t9 : 1; member
138 "Format", dw0.format, "Type", dw0.type, "T9", dw0.t9, in hisi_ptt_4dw_print_dw0()
/linux/tools/include/nolibc/
H A Darch-mips.h39 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", "t8", "t9"
197 "lui $t9, %hi(_start_c)\n" /* ABI requires current function address in $t9 */ in __start()
198 "ori $t9, %lo(_start_c)\n" in __start()
199 "jalr $t9\n" /* transfer to c runtime */ in __start()
/linux/arch/mips/loongson64/
H A Dsleeper.S14 move t9, a0
17 jalr t9
/linux/arch/alpha/lib/
H A Dstxcpy.S13 * t9 = return address
39 .frame sp, 0, t9
91 ret (t9) # .. e1 :
99 .frame sp, 0, t9
230 ret (t9) # .. e1 :
288 ret (t9) # e1 :
H A Dev6-stxcpy.S13 * t9 = return address
50 .frame sp, 0, t9
109 ret (t9) # L0 : Latency=3
119 .frame sp, 0, t9
259 ret (t9) # L0 : Latency=3
318 ret (t9) # e1 :
H A Dstxncpy.S14 * t9 = return address
47 .frame sp, 0, t9, 0
105 ret (t9) # e1 :
118 .frame sp, 0, t9, 0
266 ret (t9) # .. e1 :
344 ret (t9) # .. e1 :
H A Dev6-stxncpy.S14 * t9 = return address
58 .frame sp, 0, t9, 0
133 ret (t9) # L0 : Latency=3
150 .frame sp, 0, t9, 0
312 ret (t9) # L0 : Latency=3
393 ret (t9) # L0 : Latency=3
/linux/arch/arm64/crypto/
H A Dghash-ce-core.S31 t9 .req v16
106 pmull\t t9.8h, \ad, \b4\().\nb // K = A*B4
115 uzp1 t6.2d, t7.2d, t9.2d
116 uzp2 t7.2d, t7.2d, t9.2d
124 // t9 = (K) (P6 + P7) << 32
133 zip2 t9.2d, t6.2d, t7.2d
139 ext t9.16b, t9.16b, t9.16b, #12
142 eor t7.16b, t7.16b, t9.16b
H A Dcrct10dif-ce-core.S89 t9 .req v23
145 pmull t9.8h, ad.8b, bd3.8b // I = A*B3
159 pmull2 t9.8h, ad.16b, bd3.16b // I = A*B3
164 eor t6.16b, t6.16b, t9.16b // N = I + J
/linux/arch/mips/vdso/
H A DMakefile60 # Check that we don't have PIC 'jalr t9' calls left
62 cmd_vdso_mips_check = if $(OBJDUMP) --disassemble $@ | grep -E -h "jalr.*t9" > /dev/null; \
63 then (echo >&2 "$@: PIC 'jalr t9' calls are not supported"; \
/linux/drivers/gpu/drm/i915/display/
H A Dintel_pps.c1329 seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off); in intel_pps_readout_hw_state()
1350 "%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", in intel_pps_dump_state()
1352 seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12); in intel_pps_dump_state()
1364 if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 || in intel_pps_verify_state()
1374 return delays->t1_t3 || delays->t8 || delays->t9 || in pps_delays_valid()
1436 spec->t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ in pps_init_delays_spec()
1470 assign_final(t9); in pps_init_delays()
1478 intel_dp->pps.backlight_off_delay = get_delay(t9); in pps_init_delays()
1495 * on them. For T8, even BSpec recommends doing it. For T9, if we in pps_init_delays()
1501 final->t9 = 1; in pps_init_delays()
[all …]
/linux/arch/mips/include/asm/
H A Dregdef.h141 #define t9 $25
184 #define t9 $25 /* callee address for PIC/temp */
/linux/arch/alpha/include/uapi/asm/
H A Dregdef.h33 #define t9 $23 macro
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8186-corsola-tentacruel-sku262144.dts27 MATRIX_KEY(0x01, 0x09, 0) /* T9 */
H A Dmt8186-corsola-tentacool-sku327681.dts35 MATRIX_KEY(0x01, 0x09, 0) /* T9 */
H A Dmt8192-asurada-hayato-r5-sku2.dts25 MATRIX_KEY(0x01, 0x09, 0) /* T9 */
H A Dmt8192-asurada-spherion-r4.dts41 MATRIX_KEY(0x01, 0x09, 0) /* T9 */

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