| /freebsd/sys/contrib/device-tree/Bindings/net/can/ |
| H A D | fsl-flexcan.txt | 1 Flexcan CAN controller on Freescale's ARM and PowerPC system-on-a-chip (SOC).
5 - compatible : Should be "fsl,<processor>-flexcan"
10 - fsl,p1010-flexcan
12 - reg : Offset and length of the register set for this device
13 - interrupts : Interrupt tuple for this device
17 - clock-frequency : The oscillator frequency driving the flexcan device
19 - xceiver-supply: Regulator that powers the CAN transceiver
21 - big-endian: This means the registers of FlexCAN controller are big endian.
27 - fsl,stop-mode: register bits of stop mode control, the format is
35 - fsl,clk-source: Select the clock source to the CAN Protocol Engine (PE).
[all …]
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| H A D | fsl,flexcan.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 Flexcan CAN controller on Freescale's ARM and PowerPC system-on-a-chip (SOC).
11 - Marc Kleine-Budde <mkl@pengutronix.de>
14 - $ref: can-controller.yaml#
19 - enum:
20 - fsl,imx95-flexcan
21 - fsl,imx93-flexcan
22 - fsl,imx8qm-flexcan
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/reset/ |
| H A D | img,pistachio-reset.txt | 5 disable individual IP blocks within the Pistachio SoC using "soft reset"
6 control bits found in the Pistachio SoC top level registers.
8 The actual action taken when soft reset is asserted is hardware dependent.
18 - compatible: Contains "img,pistachio-reset"
20 - #reset-cells: Contains 1
25 compatible = "img,pistachio-cr-periph", "syscon", "simple-mfd";
28 clock-names = "sys";
29 #clock-cells = <1>;
31 pistachio_reset: reset-controller {
32 compatible = "img,pistachio-reset";
[all …]
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| H A D | st,stih407-picophyreset.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/st,stih407-picophyreset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Griffin <peter.griffin@linaro.org>
14 disable on-chip PicoPHY USB2 phy(s) using "softreset" control bits found in
15 the STi family SoC system configuration registers.
17 The actual action taken when softreset is asserted is hardware dependent.
24 const: st,stih407-picophyreset
26 '#reset-cells':
[all …]
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| H A D | st,stih407-powerdown.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/st,stih407-powerdown.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@st.com>
14 disable on-chip peripheral controllers such as USB and SATA, using
15 "powerdown" control bits found in the STi family SoC system configuration
19 The actual action taken when powerdown is asserted is hardware dependent.
26 const: st,stih407-powerdown
28 '#reset-cells':
[all …]
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| H A D | st,sti-picophyreset.txt | 5 disable on-chip PicoPHY USB2 phy(s) using "softreset" control bits found in
6 the STi family SoC system configuration registers.
8 The actual action taken when softreset is asserted is hardware dependent.
17 - compatible: Should be "st,stih407-picophyreset"
18 - #reset-cells: 1, see below
22 picophyreset: picophyreset-controller {
23 compatible = "st,stih407-picophyreset";
24 #reset-cells = <1>;
42 include/dt-bindings/reset/stih407-resets.h
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| H A D | st,sti-powerdown.txt | 5 disable on-chip peripheral controllers such as USB and SATA, using
6 "powerdown" control bits found in the STi family SoC system configuration
10 The actual action taken when powerdown is asserted is hardware dependent.
19 - compatible: Should be "st,stih407-powerdown"
20 - #reset-cells: 1, see below
24 powerdown: powerdown-controller {
25 compatible = "st,stih407-powerdown";
26 #reset-cells = <1>;
45 include/dt-bindings/reset/stih407-resets.h
|
| H A D | st,sti-softreset.txt | 5 disable on-chip peripheral controllers such as USB and SATA, using
6 "softreset" control bits found in the STi family SoC system configuration
9 The actual action taken when softreset is asserted is hardware dependent.
18 - compatible: Should be "st,stih407-softreset";
19 - #reset-cells: 1, see below
23 softreset: softreset-controller {
24 #reset-cells = <1>;
25 compatible = "st,stih407-softreset";
44 include/dt-bindings/reset/stih407-resets.h
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| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | sti-dwmac.txt | 1 STMicroelectronics SoC DWMAC glue layer controller
10 - compatible : "st,stih407-dwmac"
11 - st,syscon : Should be phandle/offset pair. The phandle to the syscon node which
13 - st,gmac_en: this is to enable the gmac into a dedicated sysctl control
14 register available on STiH407 SoC.
15 - pinctrl-0: pin-control for all the MII mode supported.
18 - reset
[all...] |
| H A D | cdns,macb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Claudiu Beznea <claudiu.beznea@microchip.com>
16 - items:
17 - enum:
18 - cdns,at91rm9200-emac # Atmel at91rm9200 SoC
19 - const: cdns,emac # Generic
21 - items:
[all …]
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| /freebsd/sys/arm/xilinx/ |
| H A D | zy7_machdep.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
30 * Machine dependent code for Xilinx Zynq-7000 Soc.
32 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
60 * Set up static device mappings. Not strictly necessary -- simplebus will
61 * dynamically establish mappings as needed -- but doing it this way gets us
99 FDT_PLATFORM_DEF(zynq7, "zynq7", 0, "xlnx,zynq-7000", 200);
|
| /freebsd/sys/contrib/device-tree/Bindings/mtd/ |
| H A D | gpmc-nand.txt | 7 explained in a separate documents - please refer to
8 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
11 Documentation/devicetree/bindings/mtd/nand-controller.yaml
16 - compatible: "ti,omap2-nand"
17 - reg: range id (CS number), base offset and length of the
19 - interrupts: Two interrupt specifiers, one for fifoevent, one for termcount.
23 - nand-bus-width: Set this numeric value to 16 if the hardware
27 - ti,nand-ecc-opt: A string setting the ECC layout to use. One of:
28 "sw" 1-bit Hamming ecc code via software
30 "hw-romcode" <deprecated> use "ham1" instead
[all …]
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| H A D | orion-nand.txt | 1 NAND support for Marvell Orion SoC platforms
4 - compatible : "marvell,orion-nand".
5 - reg : Base physical address of the NAND and length of memory mapped
9 - cle : Address line number connected to CLE. Default is 0
10 - ale : Address line number connected to ALE. Default is 1
11 - bank-width : Width in bytes of the device. Default is 1
12 - chip-delay : Chip dependent delay for transferring data from array to read
15 The device tree may optionally contain sub-nodes describing partitions of the
21 #address-cells = <1>;
22 #size-cells = <1>;
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/phy/ |
| H A D | samsung-phy.txt | 1 Samsung S5P/Exynos SoC series MIPI CSIS/DSIM DPHY
2 -------------------------------------------------
5 - compatible : should be one of the listed compatibles:
6 - "samsung,s5pv210-mipi-video-phy"
7 - "samsung,exynos5420-mipi-video-phy"
8 - "samsung,exynos5433-mipi-video-phy"
9 - #phy-cells : from the generic phy bindings, must be 1;
12 - syscon - phandle to the PMU system controller
15 - samsung,pmu-syscon - phandle to the PMU system controller
16 - samsung,disp-sysreg - phandle to the DISP system registers controller
[all …]
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| H A D | samsung,usb2-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,usb2-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S5P/Exynos SoC USB 2.0 PHY
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Marek Szyprowski <m.szyprowski@samsung.com>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
16 meaning is compatible dependent. For the currently supported SoCs (Exynos4210
18 0 - USB device ("device"),
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/media/ |
| H A D | nxp,imx8-isi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nxp,imx8-isi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
16 number and nature is SoC-dependent. They cover both capture interfaces (MIPI
17 CSI-2 RX, HDMI RX, ...) and display engine outputs for writeback support.
22 - fsl,imx8mn-isi
23 - fsl,imx8mp-isi
24 - fsl,imx93-isi
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/dma/ |
| H A D | socionext,uniphier-mio-dmac.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/dma/socionext,uniphier-mio-dmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Masahiro Yamada <yamada.masahiro@socionext.com>
17 - $ref: dma-controller.yaml#
21 const: socionext,uniphier-mio-dmac
29 The number of interrupt lines is SoC-dependent.
37 '#dma-cells':
42 - compatible
[all …]
|
| /freebsd/sys/arm64/conf/ |
| H A D | NOTES | 2 # NOTES -- Lines that can be cut/pasted into kernel and hints configs.
4 # This file contains machine dependent kernel configuration notes. For
25 makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols
30 options VFP # Floating-point support
33 # SoC support
69 # Microsoft Hyper-V
80 device al_pci # Annapurna Alpine PCI-E
81 options PCI_HP # PCI-Express native HotPlug
82 options PCI_IOV # PCI SR-IOV support
102 # Broadcom MPT Fusion, version 4, is 64-bit only
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/mailbox/ |
| H A D | omap-mailbox.txt | 14 fixed for an instance and are dictated by the IP integration into the SoC
22 All the current OMAP SoCs except for the newest DRA7xx SoC has a single IP
25 routed to different processor sub-systems on DRA7xx as they are routed through
38 a SoC. The sub-mailboxes are represented as child nodes of this parent node.
41 --------------------
42 - compatible: Should be one of the following,
43 "ti,omap2-mailbox" for OMAP2420, OMAP2430 SoCs
44 "ti,omap3-mailbox" for OMAP3430, OMAP3630 SoCs
45 "ti,omap4-mailbox" for OMAP44xx, OMAP54xx, AM33xx,
47 "ti,am654-mailbox" for K3 AM65x and J721E SoCs
[all …]
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| H A D | ti,omap-mailbox.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/ti,omap-mailbo
[all...] |
| H A D | arm,mhuv2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tushar Khandelwal <tushar.khandelwal@arm.com>
11 - Viresh Kumar <viresh.kumar@linaro.org>
15 between 1 and 124 channel windows (each 32-bit wide) to provide unidirectional
17 are implementation dependent.
33 - Data-transfer: Each transfer is made of one or more words, using one or more
36 - Doorbell: Each transfer is made up of single bit flag, using any one of the
49 - arm,mhuv2-tx
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/display/ |
| H A D | renesas,du.txt | 1 * Renesas R-Car Display Unit (DU)
5 - compatible: must be one of the following.
6 - "renesas,du-r8a7742" for R8A7742 (RZ/G1H) compatible DU
7 - "renesas,du-r8a7743" for R8A7743 (RZ/G1M) compatible DU
8 - "renesas,du-r8a7744" for R8A7744 (RZ/G1N) compatible DU
9 - "renesas,du-r8a7745" for R8A7745 (RZ/G1E) compatible DU
10 - "renesas,du-r8a77470" for R8A77470 (RZ/G1C) compatible DU
11 - "renesas,du-r8a774a1" for R8A774A1 (RZ/G2M) compatible DU
12 - "renesas,du-r8a774b1" for R8A774B1 (RZ/G2N) compatible DU
13 - "renesas,du-r8a774c0" for R8A774C0 (RZ/G2E) compatible DU
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/soc/qcom/ |
| H A D | rpmh-rsc.txt | 2 ------------
12 active/wake resource requests. Multiple such DRVs can exist in a SoC and can
17 have powered off to facilitate idle power saving. TCS could be classified as -
35 - compatible:
38 Definition: Should be "qcom,rpmh-rsc".
40 - reg:
42 Value type: <prop-encoded-array>
44 DRV(s). The number of DRVs in the dependent on the RSC.
45 The tcs-offset specifies the start address of the
48 - reg-names:
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
| H A D | renesas,rzg2l-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
16 Pin multiplexing and GPIO configuration is performed on a per-pin basis.
24 - items:
25 - enum:
26 - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five
[all …]
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| /freebsd/sys/contrib/device-tree/src/arm64/qcom/ |
| H A D | sc7280-qcard.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
14 #include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
15 #include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h>
16 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
17 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
21 /* PMICs depend on spmi_bus label and so must come after SoC */
34 wcd9385: audio-codec-1 {
35 compatible = "qcom,wcd9385-codec";
36 pinctrl-names = "default", "sleep";
37 pinctrl-0 = <&wcd_reset_n>, <&us_euro_hs_sel>;
[all …]
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