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/linux/Documentation/devicetree/bindings/media/i2c/
H A Dst,st-mipid02.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/i2c/st,st-mipid02.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
10 - Benjamin Mugnier <benjamin.mugnier@foss.st.com>
11 - Sylvain Petinot <sylvain.petinot@foss.st.com>
14 MIPID02 has two CSI-2 input ports, only one of those ports can be
15 active at a time. Active port input stream will be de-serialized
17 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2
[all …]
/linux/drivers/gpu/drm/i915/display/
H A Dintel_cx0_phy_regs.h1 /* SPDX-License-Identifier: MIT
20 * single range, starting with the TC offsets. When used together with
21 * _PICK_EVEN_2RANGES(idx, PORT_TC1, ...), this single range will be the second
24 * PORT_TC1 -> PORT_TC1
25 * PORT_TC2 -> PORT_TC2
26 * PORT_TC3 -> PORT_TC3
27 * PORT_TC4 -> PORT_TC4
28 * PORT_A -> PORT_TC4 + 1
29 * PORT_B -> PORT_TC4 + 2
33 (port >= PORT_TC1 ? port : PORT_TC4 + 1 + port - PORT_A)
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H A Dintel_dpio_phy.c2 * Copyright © 2014-2016 Intel Corporation
46 * IOSF-SB port.
49 * houses a common lane part which contains the PLL and other common
50 * logic. CH0 common lane also contains the IOSF-SB logic for the
60 * each spline is made up of one Physical Access Coding Sub-Layer
65 * Additionally the PHY also contains an AUX lane with AUX blocks
71 * Generally on VLV/CHV the common lane corresponds to the pipe and
87 * For single channel PHY (CHV):
104 * ---------------------------------
107 * |---------------|---------------| Display PHY
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/linux/Documentation/devicetree/bindings/phy/
H A Dnvidia,tegra210-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 signals) which connect directly to pins/pads on the SoC package. Each lane
18 and thus contains any logic common to all its lanes. Each lane can be
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
[all …]
H A Dnvidia,tegra194-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 signals) which connect directly to pins/pads on the SoC package. Each lane
18 and thus contains any logic common to all its lanes. Each lane can be
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
[all …]
H A Dnvidia,tegra186-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 signals) which connect directly to pins/pads on the SoC package. Each lane
18 and thus contains any logic common to all its lanes. Each lane can be
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
[all …]
H A Dnvidia,tegra124-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 signals) which connect directly to pins/pads on the SoC package. Each lane
18 and thus contains any logic common to all its lanes. Each lane can be
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
[all …]
H A Dphy-cadence-torrent.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Swapnil Jakhade <sjakhade@cadence.com>
17 - Yuti Amonkar <yamonkar@cadence.com>
22 - cdns,torrent-phy
23 - ti,j7200-serdes-10g
24 - ti,j721e-serdes-10g
26 '#address-cells':
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/linux/Documentation/devicetree/bindings/display/bridge/
H A Dtoshiba,tc358775.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinay Simha BN <simhavcs@gmail.com>
15 MIPI DSI-RX Data 4-lane, CLK 1-lane with data rates up to 800 Mbps/lane.
17 Up to 1600x1200 24-bit/pixel resolution for single-link LVDS display panel
19 Up to WUXGA (1920x1200 24-bit pixels) resolution for dual-link LVDS display
25 - toshiba,tc358765
26 - toshiba,tc358775
32 vdd-supply:
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H A Dti,sn65dsi83.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Vasut <marex@denx.de>
13 Texas Instruments SN65DSI83 1x Single-link MIPI DSI
14 to 1x Single-link LVDS
16 Texas Instruments SN65DSI84 1x Single-link MIPI DSI
17 to 1x Dual-link or 2x Single-link LVDS
23 - ti,sn65dsi83
24 - ti,sn65dsi84
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H A Dps8640.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Boichat <drinkcat@chromium.org>
13 The PS8640 is a low power MIPI-to-eDP video format converter supporting
15 device accepts a single channel of MIPI DSI v1.1, with up to four lanes
16 plus clock, at a transmission rate up to 1.5Gbit/sec per lane. The
18 3.24Gbit/sec per lane.
28 powerdown-gpios:
32 reset-gpios:
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/linux/drivers/gpu/drm/bridge/
H A Dtc358775.c1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/media-bus-format.h>
36 /* DSI D-PHY Layer Registers */
37 #define D0W_DPHYCONTTX 0x0004 /* Data Lane 0 DPHY Tx Control */
38 #define CLW_DPHYCONTRX 0x0020 /* Clock Lane DPHY Rx Control */
39 #define D0W_DPHYCONTRX 0x0024 /* Data Lane 0 DPHY Rx Control */
40 #define D1W_DPHYCONTRX 0x0028 /* Data Lane 1 DPHY Rx Control */
41 #define D2W_DPHYCONTRX 0x002C /* Data Lane 2 DPHY Rx Control */
42 #define D3W_DPHYCONTRX 0x0030 /* Data Lane 3 DPHY Rx Control */
44 #define CLW_CNTRL 0x0040 /* Clock Lane Control */
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/linux/drivers/edac/
H A Dthunderx_edac.c8 * Copyright Cavium, Inc. (C) 2015-2017. All rights reserved.
50 while (descr->type && descr->mask && descr->descr) { in decode_register()
51 if (reg & descr->mask) { in decode_register()
53 descr->type == ERR_CORRECTED ? in decode_register()
55 descr->descr); in decode_register()
57 size -= ret; in decode_register()
65 return (data >> pos) & ((1 << width) - 1); in get_bits()
121 .descr = "Single-bit ECC error",
131 .descr = "Double-bit ECC error",
136 .descr = "Non-existent memory write",
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/linux/drivers/gpu/drm/gma500/
H A Dcdv_intel_dp.c45 * struct i2c_algo_dp_aux_data - driver interface structure for i2c over dp
50 * @aux_ch: driver callback to transfer a single byte of the i2c payload
60 /* Run a single AUX_CH I2C transaction, writing/reading data as necessary */
65 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; in i2c_algo_dp_aux_transaction()
68 ret = (*algo_data->aux_ch)(adapter, mode, in i2c_algo_dp_aux_transaction()
85 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; in i2c_algo_dp_aux_address()
92 algo_data->address = address; in i2c_algo_dp_aux_address()
93 algo_data->running = true; in i2c_algo_dp_aux_address()
104 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; in i2c_algo_dp_aux_stop()
111 if (algo_data->running) { in i2c_algo_dp_aux_stop()
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/linux/drivers/thunderbolt/
H A Dclx.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020 - 2023, Intel Corporation
16 MODULE_PARM_DESC(clx, "allow low power states on the high-speed lanes (default: true)");
44 port->cap_phy + LANE_ADP_CS_1, 1); in tb_port_pm_secondary_set()
54 port->cap_phy + LANE_ADP_CS_1, 1); in tb_port_pm_secondary_set()
73 /* Don't enable CLx in case of two single-lane links */ in tb_port_clx_supported()
74 if (!port->bonded && port->dual_link_port) in tb_port_clx_supported()
77 /* Don't enable CLx in case of inter-domain link */ in tb_port_clx_supported()
78 if (port->xdomain) in tb_port_clx_supported()
81 if (tb_switch_is_usb4(port->sw)) { in tb_port_clx_supported()
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/linux/drivers/net/ethernet/sfc/falcon/
H A Dtxc43128_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright 2006-2011 Solarflare Communications Inc.
9 * see www.transwitch.com, part is TXC-43128
30 * Compile-time config
52 /* Lane power-down */
56 * initiates a logic reset. Self-clearing */
63 /* Lane selection */
69 /* Lane power-down */
79 /* Bit position of value for lane 0 (or 2) */
81 /* Bit position of value for lane 1 (or 3) */
[all …]
/linux/tools/perf/pmu-events/arch/x86/sapphirerapids/
H A Duncore-io.json182 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7",
190 "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7",
203 …ompletions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
216 …ompletions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
229 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
242 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
255 …ompletions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
268 …ompletions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
281 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
294 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
[all …]
/linux/tools/perf/pmu-events/arch/x86/emeraldrapids/
H A Duncore-io.json182 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7",
190 "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7",
203 …ompletions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
216 …ompletions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
229 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
242 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
255 …ompletions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
268 …ompletions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
281 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
294 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dnvidia,tegra124-xusb-padctl.txt7 needed for USB. For the new binding, see ../phy/nvidia,tegra-xusb-padctl.txt.
14 This document defines the device-specific binding for the XUSB pad controller.
16 Refer to pinctrl-bindings.txt in this directory for generic information about
17 pin controller device tree bindings and ../phy/phy-bindings.txt for details on
21 --------------------
22 - compatible: For Tegra124, must contain "nvidia,tegra124-xusb-padctl".
23 Otherwise, must contain '"nvidia,<chip>-xusb-padctl",
24 "nvidia-tegra124-xusb-padctl"', where <chip> is tegra132 or tegra210.
25 - reg: Physical base address and length of the controller's registers.
26 - resets: Must contain an entry for each entry in reset-names.
[all …]
/linux/drivers/phy/
H A Dphy-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
23 * | | | | ---------
24 * External Clock ------| | -------------
25 * |------|
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/linux/Documentation/driver-api/nvdimm/
H A Dbtt.rst2 BTT - Block Translation Table
14 using stored energy in capacitors to complete in-flight block writes, or perhaps
15 in firmware. We don't have this luxury with persistent memory - if a write is in
23 the heart of it, is an indirection table that re-maps all the blocks on the
37 next arena). The following depicts the "On-disk" metadata layout::
40 Backing Store +-------> Arena
41 +---------------+ | +------------------+
43 | Arena 0 +---+ | 4K |
44 | 512G | +------------------+
46 +---------------+ | |
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/linux/drivers/gpu/drm/amd/display/dc/link/protocols/
H A Dlink_dp_irq_handler.c42 link->ctx->logger
52 uint32_t lane; in dp_parse_link_loss_status() local
59 if (link->cur_link_settings.lane_count == 0) in dp_parse_link_loss_status()
62 /*1. Check that Link Status changed, before re-training.*/ in dp_parse_link_loss_status()
64 /*parse lane status*/ in dp_parse_link_loss_status()
65 for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) { in dp_parse_link_loss_status()
70 &hpd_irq_dpcd_data->bytes.lane01_status.raw, in dp_parse_link_loss_status()
71 lane); in dp_parse_link_loss_status()
87 if (link_dp_get_encoding_format(&link->cur_link_settings) == DP_128b_132b_ENCODING && in dp_parse_link_loss_status()
88 (!hpd_irq_dpcd_data->bytes.lane_status_updated.bits.EQ_INTERLANE_ALIGN_DONE_128b_132b || in dp_parse_link_loss_status()
[all …]
/linux/drivers/gpu/drm/bridge/analogix/
H A Danalogix_dp_core.c1 // SPDX-License-Identifier: GPL-2.0-or-later
72 * "force-hpd" would indicate whether driver need this. in analogix_dp_detect_hpd()
74 if (!dp->force_hpd) in analogix_dp_detect_hpd()
75 return -ETIMEDOUT; in analogix_dp_detect_hpd()
82 dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n"); in analogix_dp_detect_hpd()
87 dev_err(dp->dev, "failed to get hpd plug in status\n"); in analogix_dp_detect_hpd()
88 return -EINVAL; in analogix_dp_detect_hpd()
91 dev_dbg(dp->dev, "success to get plug in status after force hpd\n"); in analogix_dp_detect_hpd()
101 ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version); in analogix_dp_detect_sink_psr()
103 dev_err(dp->dev, "failed to get PSR version, disable it\n"); in analogix_dp_detect_sink_psr()
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/linux/arch/arm64/boot/dts/ti/
H A Dk3-am654-pcie-usb2.dtso1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * DT overlay for SERDES personality card: 2lane PCIe + USB2.0 Host on AM654 EVM
5 * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/phy/phy-am654-serdes.h>
13 #include "k3-pinctrl.h"
16 assigned-clocks = <&k3_clks 153 4>,
19 assigned-clock-parents = <&k3_clks 153 8>,
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/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A Duncore-io.json13 …, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
29 …, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
145 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7",
152 "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7",
164 …ompletions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
176 …ompletions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
188 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
200 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
212 …ompletions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
224 …ompletions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
[all …]

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