| /freebsd/sys/contrib/device-tree/Bindings/media/i2c/ |
| H A D | st,st-mipid02.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/i2c/st,st-mipid0
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| H A D | st,st-mipid02.txt | 1 STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
3 MIPID02 has two CSI-2 input ports, only one of those ports can be active at a
4 time. Active port input stream will be de-serialized and its content outputted
6 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 second
7 input port is a single lane 800Mbps. Both ports support clock and data lane
8 polarity swap. First port also supports data lane swap.
11 YUV420 8-bit, YUV422 8-bit and YUV420 10-bit.
14 - compatible: shall be "st,st-mipid02"
15 - clocks: reference to the xclk input clock.
16 - clock-names: shall be "xclk".
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| H A D | ov2680.txt | 1 * Omnivision OV2680 MIPI CSI-2 sensor
4 - compatible: should be "ovti,ov2680".
5 - clocks: reference to the xvclk input clock.
6 - clock-names: should be "xvclk".
7 - DOVDD-supply: Digital I/O voltage supply.
8 - DVDD-supply: Digital core voltage supply.
9 - AVDD-supply: Analog voltage supply.
12 - reset-gpios: reference to the GPIO connected to the powerdown/reset pin,
16 video port, and this port must have a single endpoint in accordance with
18 Documentation/devicetree/bindings/media/video-interfaces.txt.
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|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUAtomicOptimizer.cpp | 1 //===-- AMDGPUAtomicOptimizer.cpp -----------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 /// This pass optimizes atomic operations by using a single lane of a wavefront
15 /// 1. DPP -
18 /// 2. Iterative -
22 //===----------------------------------------------------------------------===//
36 #define DEBUG_TYPE "amdgpu-atomic-optimizer"
123 DomTreeUpdater DTU(DTW ? &DTW->getDomTree() : nullptr, in runOnFunction()
182 switch (Ty->getTypeID()) { in isLegalCrossLaneType()
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| /freebsd/sys/contrib/alpine-hal/ |
| H A D | al_hal_serdes_internal_regs.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
44 * Per lane register fields
47 * RX and TX lane hard reset
48 * 0 - Hard reset is asserted
49 * 1 - Hard reset is de-asserted
57 * RX and TX lane hard reset control
58 * 0 - Hard reset is taken from the interface pins
59 * 1 - Hard reset is taken from registers
66 /* RX lane power state control */
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| H A D | al_hal_serdes_hssp_internal_regs.h | 9 found at http://www.gnu.org/licenses/gpl-2.0.html
43 * Per lane register fields
46 * RX and TX lane hard reset
47 * 0 - Hard reset is asserted
48 * 1 - Hard reset is de-asserted
56 * RX and TX lane hard reset control
57 * 0 - Hard reset is taken from the interface pins
58 * 1 - Hard reset is taken from registers
65 /* RX lane power state control */
74 /* TX lane power state control */
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| H A D | al_hal_serdes_interface.h | 9 found at http://www.gnu.org/licenses/gpl-2.0.html
53 /* *INDENT-OFF* */
57 /* *INDENT-ON* */
120 * Parallel loopback from the PMA receive lane data ports, to the
121 * transmit lane data ports
178 * Tx de-emphasis parameters
183 AL_SERDES_TX_DEEMP_C_MINUS, /*< c(-1) */
196 * Transmit Amplitude control signal. Used to define the full-scale
198 * 000 - Not Supported
199 * 001 - 952mVdiff-pkpk
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | VPlan.h | 1 //===- VPlan.h - Represent A Vectorizer Plan --------------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
17 /// 4. VPInstruction, a concrete Recipe and VPUser modeling a single planned
23 //===----------------------------------------------------------------------===//
97 /// A range of powers-of-2 vectorization factors with fixed start and
154 /// vectors, where for the latter the lane index sometimes needs calculating
158 /// Kind describes how to interpret Lane.
160 /// For First, Lane is the index into the first N elements of a
161 /// fixed-vector <N x <ElTy>> or a scalable vector <vscale x N x <ElTy>>.
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| H A D | VPlan.cpp | 1 //===- VPlan.cpp - Vectorizer Plan ----------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 /// before generating LLVM-IR.
15 /// LLVM-IR code.
17 //===----------------------------------------------------------------------===//
64 (Instr && Instr->getParent()) ? Instr->getParent()->getPlan() : nullptr); in operator <<()
74 // Lane = RuntimeVF - VF.getKnownMinValue() + Lane in getAsRuntimeExpr()
76 Builder.getInt32(VF.getKnownMinValue() - Lane)); in getAsRuntimeExpr()
78 return Builder.getInt32(Lane); in getAsRuntimeExpr()
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| /freebsd/sys/contrib/device-tree/Bindings/phy/ |
| H A D | nvidia,tegra210-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xus
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| H A D | nvidia,tegra194-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 signals) which connect directly to pins/pads on the SoC package. Each lane
18 and thus contains any logic common to all its lanes. Each lane can be
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
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|
| H A D | nvidia,tegra186-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 signals) which connect directly to pins/pads on the SoC package. Each lane
18 and thus contains any logic common to all its lanes. Each lane can be
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
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|
| H A D | phy-cadence-sierra.txt | 2 -----------------------
5 - compatible: Must be "cdns,sierra-phy-t0" for Sierra in Cadence platform
6 Must be "ti,sierra-phy-t0" for Sierra in TI's J721E SoC.
7 - resets: Must contain an entry for each in reset-names.
9 - reset-names: Must include "sierra_reset" and "sierra_apb".
13 - reg: register range for the PHY.
14 - #address-cells: Must be 1
15 - #size-cells: Must be 0
18 - clocks: Must contain an entry in clock-names.
19 See ../clocks/clock-bindings.txt for details.
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| H A D | nvidia,tegra124-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 signals) which connect directly to pins/pads on the SoC package. Each lane
18 and thus contains any logic common to all its lanes. Each lane can be
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
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|
| H A D | phy-cadence-sierra.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-cadence-sierra.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Swapnil Jakhade <sjakhade@cadence.com>
15 - Yuti Amonkar <yamonkar@cadence.com>
20 - cdns,sierra-phy-t0
21 - ti,sierra-phy-t0
23 '#address-cells':
26 '#size-cells':
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|
| H A D | qcom,msm8996-qmp-usb3-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,msm8996-qmp-usb
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| H A D | qcom,qmp-usb-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,qmp-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinod Koul <vkoul@kernel.org>
19 - qcom,ipq6018-qmp-usb3-phy
20 - qcom,ipq8074-qmp-usb3-phy
21 - qcom,msm8996-qmp-usb3-phy
22 - qcom,msm8998-qmp-usb3-phy
23 - qcom,qcm2290-qmp-usb3-phy
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| H A D | phy-cadence-torrent.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Swapnil Jakhade <sjakhade@cadence.com>
17 - Yuti Amonkar <yamonkar@cadence.com>
22 - cdns,torrent-phy
23 - ti,j7200-serdes-10g
24 - ti,j721e-serdes-10g
26 '#address-cells':
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| H A D | qcom,qmp-ufs-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,qmp-ufs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinod Koul <vkoul@kernel.org>
19 - qcom,msm8996-qmp-ufs-phy
20 - qcom,msm8998-qmp-ufs-phy
21 - qcom,sc8180x-qmp-ufs-phy
22 - qcom,sc8280xp-qmp-ufs-phy
23 - qcom,sdm845-qmp-ufs-phy
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|
| H A D | qcom,msm8996-qmp-ufs-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,msm8996-qmp-ufs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinod Koul <vkoul@kernel.org>
17 qcom,sc8280xp-qmp-ufs-phy.yaml.
22 - qcom,msm8996-qmp-ufs-phy
23 - qcom,msm8998-qmp-ufs-phy
24 - qcom,sc8180x-qmp-ufs-phy
25 - qcom,sdm845-qmp-ufs-phy
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| /freebsd/sys/contrib/openzfs/module/zfs/ |
| H A D | zio_inject.c | 9 * or https://opensource.org/licenses/CDDL-1.0.
25 * Copyright (c) 2024-2025, Klara, Inc.
138 if (zb->zb_objset == DMU_META_OBJSET && in zio_match_handler()
139 record->zi_objset == DMU_META_OBJSET && in zio_match_handler()
140 record->zi_object == DMU_META_DNODE_OBJECT) { in zio_match_handler()
141 if (record->zi_type == DMU_OT_NONE || in zio_match_handler()
142 type == record->zi_type) in zio_match_handler()
150 if (zb->zb_objset == record->zi_objset && in zio_match_handler()
151 zb->zb_objec in zio_match_handler()
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| /freebsd/sys/contrib/device-tree/Bindings/display/bridge/ |
| H A D | toshiba,tc358775.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinay Simha BN <simhavcs@gmail.com>
15 MIPI DSI-RX Data 4-lane, CLK 1-lane with data rates up to 800 Mbps/lane.
17 Up to 1600x1200 24-bit/pixel resolution for single-link LVDS display panel
19 Up to WUXGA (1920x1200 24-bit pixels) resolution for dual-link LVDS display
25 - toshiba,tc358765
26 - toshiba,tc358775
32 vdd-supply:
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| H A D | ti,sn65dsi83.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Vasut <marex@denx.de>
13 Texas Instruments SN65DSI83 1x Single-link MIPI DSI
14 to 1x Single-link LVDS
16 Texas Instruments SN65DSI84 1x Single-link MIPI DSI
17 to 1x Dual-link or 2x Single-link LVDS
23 - ti,sn65dsi83
24 - ti,sn65dsi84
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|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstrNEON.td | 1 //===-- ARMInstrNEON.td - NEON support for ARM -------------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific Operands.
16 //===----------------------------------------------------------------------===//
256 // Register list of one D register, with byte lane subscripting.
266 // ...with half-word lane subscripting.
276 // ...with word lane subscripting.
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| /freebsd/sys/contrib/openzfs/man/man8/ |
| H A D | zinject.8 | 9 .\" or https://opensource.org/licenses/CDDL-1.0.
24 .\" lint-ok: WARNING: sections out of conventional order: Sh SYNOPSIS
40 .Bl -tag -width Ds
85 For example, with a single lane delay of 10 ms
87 the device will only be able to service a single I/O request
89 So, if only a single request is submitted every 10 ms, the
107 are roughly equivalent to a single invocation of
115 will create 3 lanes on the device: one lane wit
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