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Searched full:src4 (Results 1 – 25 of 42) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A D	X86InstrAMX.td	`75 TILE:$src4), []>; 120 let isPseudo = true, Constraints = "$src4 = $dst" in { 122 GR16:$src2, GR16:$src3, TILE:$src4, 126 GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>; 128 GR16:$src2, GR16:$src3, TILE:$src4, 132 GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>; 134 GR16:$src2, GR16:$src3, TILE:$src4, 138 GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>; 140 GR16:$src2, GR16:$src3, TILE:$src4, 144 GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>; [all …]`
H A D	X86InstrXOP.td	`421 (ins RC:$src1, RC:$src2, RC:$src3, u4imm:$src4), 423 "\t{$src4, $src3, $src2, $src1, $dst\|$dst, $src1, $src2, $src3, $src4}"), 425 (VT (X86vpermil2 RC:$src1, RC:$src2, RC:$src3, (i8 timm:$src4))))]>, 428 (ins RC:$src1, RC:$src2, intmemop:$src3, u4imm:$src4), 430 "\t{$src4, $src3, $src2, $src1, $dst\|$dst, $src1, $src2, $src3, $src4}"), 433 (i8 timm:$src4))))]>, REX_W, 436 (ins RC:$src1, fpmemop:$src2, RC:$src3, u4imm:$src4), 438 "\t{$src4, [all...]`
H A D	X86InstrAVX512.td	11725 (ins _.RC:$src2, _.RC:$src3, u8imm:$src4), 11726 OpcodeStr, "$src4, $src3, $src2", "$src2, $src3, $src4", 11730 (i8 timm:$src4)), 1, 1>, 11733 (ins _.RC:$src2, _.MemOp:$src3, u8imm:$src4), 11734 OpcodeStr, "$src4, $src3, $src2", "$src2, $src3, $src4", 11738 (i8 timm:$src4)), 1, 0>, 11742 (ins _.RC:$src2, _.ScalarMemOp:$src3, u8imm:$src4), 11743 OpcodeStr, "$src4, ${src3}"#_.BroadcastStr#", $src2", 11744 "$src2, ${src3}"#_.BroadcastStr#", $src4", 11748 (i8 timm:$src4)), 1, 0>, EVEX_B, [all …]
H A D	X86InstrSSE.td	`8384 (ins VR128:$src1, VR128:$src2, VR128:$src3, i32u8imm:$src4), 8385 "vsm3rnds2\t{$src4, $src3, $src2, $dst\|$dst, $src2, $src3, $src4}", 8388 VR128:$src2, VR128:$src3, timm:$src4))]>, 8391 (ins VR128:$src1, VR128:$src2, i128mem:$src3, i32u8imm:$src4), 8392 "vsm3rnds2\t{$src4, $src3, $src2, $dst\|$dst, $src2, $src3, $src4}", 8395 VR128:$src2, (loadv4i32 addr:$src3), timm:$src4))]>,`
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A D	HexagonMapAsm2IntrinV62.gen.td	`114 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4), 115 (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>; 117 HvxVR:$src3, imm:$src4), 118 (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>; 122 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4), 123 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>; 125 HvxVR:$src3, imm:$src4), 126 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>;`
H A D	HexagonIntrinsicsV60.td	271 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, imm:$src4), 272 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, imm:$src4)>; 275 IntRegs:$src3, imm:$src4), 276 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, imm:$src4)>; 280 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4), 281 (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>; 284 HvxVR:$src3, IntRegs:$src4), 285 (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>; 289 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4), 290 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>; [all …]
H A D	HexagonDepMapAsm2Intrin.td	612 def: Pat<(int_hexagon_F2_sffma_sc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3, PredRegs:$src4), 613 …(F2_sffma_sc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3, (C2_tfrrp PredRegs:$src4))>, Requires<[H… 1418 …nt_hexagon_S2_insert IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3, u5_0ImmPred_timm:$src4), 1419 …(S2_insert IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3, u5_0ImmPred_timm:$src4)>, Require… 1422 …gon_S2_insertp DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3, u6_0ImmPred_timm:$src4), 1423 …leRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3, u6_0ImmPred_timm:$src4)>, Requires<[HasV5]… 1642 …exagon_S4_vrcrotate_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3, u2_0ImmPred_timm:$src4), 1643 …_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3, u2_0ImmPred_timm:$src4)>, Requires<[HasV5]… 2417 def: Pat<(int_hexagon_V6_vlutvvb_oracc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4), 2418 …(V6_vlutvvb_oracc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4)>, Requires<[UseHVXV60,… [all …]
H A D	HexagonIntrinsicsV5.td	`184 IntRegs:$src3, u2_0ImmPred:$src4), 186 IntRegs:$src3, u2_0ImmPred:$src4)>;`
H A D	HexagonIntrinsics.td	`145 : Pat <(IntID I32:$src1, I32:$src2, u4_0ImmPred_timm:$src3, u5_0ImmPred_timm:$src4), 147 (XformImm u5_0ImmPred:$src4))>;`
/freebsd/sys/contrib/openzfs/module/zfs/
H A D	vdev_raidz_math_powerpc_altivec_common.h	`150 "lvx 21,0,%[SRC4]\n" \ 164 [SRC4] "r" ((OFFSET(src, 64))), \ 295 "lvx " VR4(r) " ,0,%[SRC4]\n" \ 305 [SRC4] "r" ((OFFSET(src, 64))), \`
H A D	vdev_raidz_math_aarch64_neon_common.h	`153 "ld1 { v21.4s },%[SRC4]\n" \ 167 [SRC4] "Q" ((OFFSET(src, 64))), \ 298 "ld1 { " VR4(r) ".4s },%[SRC4]\n" \ 308 [SRC4] "Q" ((OFFSET(src, 64))), \`
/freebsd/sys/net/
H A D	if_stf.c	`500 struct sockaddr_in dst4, src4; in stf_output() local 594 src4.sin_addr.s_addr = sc->srcv4_addr; in stf_output() 595 else if (stf_getin4addr(sc, &src4, addr6, mask6) == NULL) { in stf_output() 601 bcopy(&src4.sin_addr, &ip->ip_src, sizeof(ip->ip_src)); in stf_output()`
/freebsd/sys/contrib/device-tree/src/arm/renesas/
H A D	r8a7778.dtsi	`290 src4: src-4 { }; label 669 "sru-src3", "sru-src4", "sru-src5",`
H A D	r8a7745-iwg22d-sodimm.dts	`295 capture = <&ssi4>, <&src4>, <&dvc1>;`
H A D	r8a7742-iwg21d-q7.dts	`392 playback = <&ssi4>, <&src4>, <&dvc1>;`
H A D	r8a7794.dtsi	`1114 src4: src-4 { label`
H A D	r8a7793.dtsi	`1132 src4: src-4 { label`
H A D	r8a7745.dtsi	`1278 src4: src-4 { label`
H A D	r8a7744.dtsi	`1348 src4: src-4 { label`
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A D	renesas,rsnd.txt	`51 &src4 &ssi4`
H A D	renesas,rsnd.yaml	`403 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, /* SRC5, SRC4 */`
/freebsd/sys/ofed/drivers/infiniband/core/
H A D	ib_cma.c	3530 struct sockaddr_in src4, dst4; in sdp_format_hdr() local 3532 src4 = (struct sockaddr_in ) cma_src_addr(id_priv); in sdp_format_hdr() 3536 sdp_hdr->src_addr.ip4.addr = src4->sin_addr.s_addr; in sdp_format_hdr() 3538 sdp_hdr->port = src4->sin_port; in sdp_format_hdr() 3566 struct sockaddr_in src4, dst4; in cma_format_hdr() local 3568 src4 = (struct sockaddr_in ) cma_src_addr(id_priv); in cma_format_hdr() 3572 cma_hdr->src_addr.ip4.addr = src4->sin_addr.s_addr; in cma_format_hdr() 3574 cma_hdr->port = src4->sin_port; in cma_format_hdr()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A D	NVPTXInstrInfo.td	3182 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4, 3186 "\t[$addr], {{$src1, $src2, $src3, $src4}};", []>; 3189 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4, 3193 "\t[$addr], {{$src1, $src2, $src3, $src4}};", []>; 3196 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4, 3200 "\t[$addr], {{$src1, $src2, $src3, $src4}};", []>; 3203 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4, 3207 "\t[$addr+$offset], {{$src1, $src2, $src3, $src4}};", []>; 3210 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4, 3214 "\t[$addr+$offset], {{$src1, $src2, $src3, $src4}};", []>; [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A D	XCoreInstrInfo.td	`519 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, GRRegs:$src4), 520 "lmul $dst1, $dst2, $src1, $src2, $src3, $src4", []>;`
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A D	ARMInstrNEON.td	1290 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, 1293 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>, 1332 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane), 1335 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb", 2081 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), 2082 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn", 2101 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u, 2102 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm", 2399 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, 2401 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn", [all …]