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/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dqcom,spi-geni-qcom.txt1 GENI based Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
3 The QUP v3 core is a GENI based AHB slave that provides a common data path
4 (an output FIFO and an input FIFO) for serial peripheral interface (SPI)
5 mini-core.
7 SPI in master mode supports up to 50MHz, up to four chip selects, programmable
11 - compatible: Must contain "qcom,geni-spi".
12 - reg: Must contain SPI register location and length.
13 - interrupts: Must contain SPI controller interrupts.
14 - clock-names: Must contain "se".
15 - clocks: Serial engine core clock needed by the device.
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H A Dbrcm,bcm63xx-hsspi.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/spi/brcm,bcm63xx-hsspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom Broadband SoC High Speed SPI controller
10 - William Zhang <william.zhang@broadcom.com>
11 - Kursad Oney <kursad.oney@broadcom.com>
12 - Jonas Gorski <jonas.gorski@gmail.com>
15 Broadcom Broadband SoC supports High Speed SPI master controller since the
16 early MIPS based chips such as BCM6328 and BCM63268. This initial rev 1.0
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H A Dqcom,spi-geni-qcom.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/qcom,spi-geni-qcom.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: GENI based Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
12 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
15 The QUP v3 core is a GENI based AHB slave that provides a common data path
16 (an output FIFO and an input FIFO) for serial peripheral interface (SPI)
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H A Dnvidia,tegra114-spi.txt1 NVIDIA Tegra114 SPI controller.
4 - compatible : For Tegra114, must contain "nvidia,tegra114-spi".
5 Otherwise, must contain '"nvidia,<chip>-spi", "nvidia,tegra114-spi"' where
7 - reg: Should contain SPI registers location and length.
8 - interrupts: Should contain SPI interrupts.
9 - clock-names : Must include the following entries:
10 - spi
11 - resets : Must contain an entry for each entry in reset-names.
13 - reset-names : Must include the following entries:
14 - spi
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H A Dmicrochip,mpfs-spi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/microchip,mpfs-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip FPGA {Q,}SPI Controllers
10 SPI and QSPI controllers on Microchip PolarFire SoC and the "soft"/
11 fabric IP cores they are based on
14 - Conor Dooley <conor.dooley@microchip.com>
19 - items:
20 - enum:
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H A Drenesas,rzn1-spi.txt1 Renesas RZ/N1 SPI Controller
3 This controller is based on the Synopsys DW Synchronous Serial Interface and
4 inherits all properties defined in snps,dw-apb-ssi.txt except for the
8 - compatible : The device specific string followed by the generic RZ/N1 string.
10 "renesas,r9a06g032-spi", "renesas,rzn1-spi"
11 "renesas,r9a06g033-spi", "renesas,rzn1-spi"
H A Dfsl-imx-cspi.txt5 - compatible :
6 - "fsl,imx1-cspi" for SPI compatible with the one integrated on i.MX1
7 - "fsl,imx21-cspi" for SPI compatible with the one integrated on i.MX21
8 - "fsl,imx27-cspi" for SPI compatible with the one integrated on i.MX27
9 - "fsl,imx31-cspi" for SPI compatible with the one integrated on i.MX31
10 - "fsl,imx35-cspi" for SPI compatible with the one integrated on i.MX35
11 - "fsl,imx51-ecspi" for SPI compatible with the one integrated on i.MX51
12 - "fsl,imx53-ecspi" for SPI compatible with the one integrated on i.MX53 and later Soc
13 - "fsl,imx8mq-ecspi" for SPI compatible with the one integrated on i.MX8MQ
14 - "fsl,imx8mm-ecspi" for SPI compatible with the one integrated on i.MX8MM
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/freebsd/sys/contrib/device-tree/Bindings/net/nfc/
H A Dnfcmrvl.txt4 - compatible: Should be:
5 - "marvell,nfc-uart" or "mrvl,nfc-uart" for UART devices
6 - "marvell,nfc-i2c" for I2C devices
7 - "marvell,nfc-spi" for SPI devices
10 - pinctrl-names: Contains only one value - "default".
11 - pintctrl-0: Specifies the pin control groups used for this controller.
12 - reset-n-io: Output GPIO pin used to reset the chip (active low).
13 - hci-muxed: Specifies that the chip is muxing NCI over HCI frames.
15 Optional UART-based chip specific properties:
16 - flow-control: Specifies that the chip is using RTS/CTS.
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/freebsd/sys/contrib/device-tree/Bindings/soc/qcom/
H A Dqcom,geni-se.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#
5 $schema: http://devicetree.org/meta-schema
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/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dmicrochip,sparx5.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lars Povlsen <lars.povlsen@microchip.com>
13 The Microchip Sparx5 SoC is a ARMv8-based used in a family of
14 gigabit TSN-capable gigabit switches.
16 The SparX-5 Ethernet switch family provides a rich set of switching
17 features such as advanced TCAM-based VLAN and QoS processing
19 TCAM-based frame processing using versatile content aware processor
27 - description: The Sparx5 pcb125 board is a modular board,
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/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dp2020rdb-pc.dtsi2 * P2020 RDB-PC Device Tree Source stub (no addresses or top-level ranges)
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
48 label = "NOR Vitesse-7385 Firmware";
49 read-only;
65 /* 11MB for JFFS2 based Root file System */
72 /* 512KB for u-boot Bootloader Image */
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H A Dp2020rdb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2009-2012 Freescale Semiconductor Inc.
8 /include/ "p2020si-pre.dtsi"
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
48 label = "NOR (RO) Vitesse-7385 Firmware";
49 read-only;
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H A Dp1024rdb.dtsi2 * P1024 RDB Device Tree Source stub (no addresses or top-level ranges)
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
48 label = "NOR Vitesse-7385 Firmware";
49 read-only;
65 /* 11MB for JFFS2 based Root file System */
72 /* 512KB for u-boot Bootloader Image */
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H A Dp1021rdb-pc.dtsi2 * P1021 RDB Device Tree Source stub (no addresses or top-level ranges)
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
48 label = "NOR Vitesse-7385 Firmware";
49 read-only;
65 /* 10.75MB for JFFS2 based Root file System */
75 read-only;
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H A Dp1010rdb.dtsi2 * P1010 RDB Device Tree Source stub (no addresses or top-level ranges)
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
57 /* 20MB for JFFS2 based Root file System */
64 /* 512KB for u-boot Bootloader Image */
65 /* 512KB for u-boot Environment Variables */
67 label = "NOR U-Boot Image";
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H A Dp1020rdb.dtsi2 * P1020 RDB Device Tree Source stub (no addresses or top-level ranges)
4 * Copyright 2011-2012 Freescale Semiconductor Inc.
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
48 label = "NOR (RO) Vitesse-7385 Firmware";
49 read-only;
56 read-only;
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/freebsd/share/man/man4/
H A Dmx25l.430 .Nd driver for SpiFlash(tm) compatible non-volatile storage devices
35 .Bd -ragged -offset indent
42 .Bd -literal -offset indent
48 driver provides support for the family of non-volatile storage
63 .Pa /dev/flash/spi? .
72 .Bl -bullet -compact
131 based system, the
134 of the SPI bus controller node.
140 The most commonly-used ones are documented below.
145 .Bl -tag -width indent
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H A Dspigen.431 .Nd SPI generic I/O device driver
36 .Bd -ragged -offset indent
37 .Cd "device spi"
45 .Bd -literal -offset indent
51 driver provides direct access to a slave device on the SPI bus.
54 device is associated with a single chip-select
56 with that chip-select line asserted.
58 SPI data transfers are inherently bi-directional; there are no separate
71 driver provides access to the SPI slave device with the following
75 .Bl -tag -width indent
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H A Dat45d.430 .Nd driver for DataFlash(tm) non-volatile storage devices
35 .Bd -ragged -offset indent
42 .Bd -literal -offset indent
48 driver provides support for the family of non-volatile storage
53 driver supports only the SPI bus versions of each AT45DB device,
75 .Bl -bullet -compact
98 based system, the
101 of the SPI bus controller node.
107 The most commonly-used ones are documented below.
112 .Bl -tag -width indent
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/freebsd/sys/contrib/device-tree/Bindings/security/tpm/
H A Dtpm_tis_spi.txt2 - compatible: should be one of the following
3 "st,st33htpm-spi"
5 "tcg,tpm_tis-spi"
6 - spi-max-frequency: Maximum SPI frequency (depends on TPMs).
9 - pinctrl-names: Contains only one value - "default".
10 - pintctrl-0: Specifies the pin control groups used for this controller.
12 Example (for ARM-based BeagleBoard xM with TPM_TIS on SPI4):
19 compatible = "tcg,tpm_tis-spi";
21 spi-max-frequency = <10000000>;
H A Dst33zp24-spi.txt4 - compatible: Should be "st,st33zp24-spi".
5 - spi-max-frequency: Maximum SPI frequency (<= 10000000).
8 - interrupts: GPIO interrupt to which the chip is connected
9 - lpcpd-gpios: Output GPIO pin used for ST33ZP24 power management D1/D2 state.
13 - pinctrl-names: Contains only one value - "default".
14 - pintctrl-0: Specifies the pin control groups used for this controller.
16 Example (for ARM-based BeagleBoard xM with ST33ZP24 on SPI4):
23 compatible = "st,st33zp24-spi";
25 spi-max-frequency = <10000000>;
27 interrupt-parent = <&gpio5>;
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/freebsd/sys/contrib/device-tree/Bindings/misc/
H A Dge-achc.txt3 A device which handles data aquisition from compatible USB based peripherals.
4 SPI is used for device management.
10 - compatible : Should be "ge,achc"
12 Required SPI properties:
14 - reg : Should be address of the device chip select within
17 - spi-max-frequency : Maximum SPI clocking speed of device in Hz, should be
22 spidev0: spi@0 {
25 spi-max-frequency = <1000000>;
/freebsd/sys/contrib/device-tree/Bindings/display/panel/
H A Dsamsung,lms397kf04.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
9 description: The datasheet claims this is based around a display controller
13 - Linus Walleij <linus.walleij@linaro.org>
16 - $ref: panel-common.yaml#
17 - $ref: /schemas/spi/spi-peripheral-props.yaml#
26 reset-gpios: true
28 vci-supply:
32 vccio-supply:
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/freebsd/sys/contrib/device-tree/Bindings/leds/
H A Dleds-spi-byte.txt1 * Single Byte SPI LED Device Driver.
3 The driver can be used for controllers with a very simple SPI protocol:
4 - one LED is controlled by a single byte on MOSI
5 - the value of the byte gives the brightness between two values (lowest to
7 - no return value is necessary (no MISO signal)
16 configured in a sub-node in the device node.
19 - compatible: should be one of
20 * "ubnt,acb-spi-led" microcontroller (SONiX 8F26E611LA) based device
23 Property rules described in Documentation/devicetree/bindings/spi/spi-bus.txt
26 LED sub-node properties:
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/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dmarvell,odmi-controller.txt4 Some Marvell SoCs have an On-Die Message Interrupt (ODMI) controller
5 which can be used by on-board peripheral for MSI interrupts.
9 - compatible : The value here should contain:
11 "marvell,ap806-odmi-controller", "marvell,odmi-controller".
13 - interrupt,controller : Identifies the node as an interrupt controller.
15 - msi-controller : Identifies the node as an MSI controller.
17 - marvell,odmi-frames : Number of ODMI frames available. Each frame
20 - reg : List of register definitions, one for each
23 - marvell,spi-base : List of GIC base SPI interrupts, one for each
24 ODMI frame. Those SPI interrupts are 0-based,
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