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/linux/Documentation/devicetree/bindings/nvmem/
H A Dsnvs-lpgpr.yaml4 $id: http://devicetree.org/schemas/nvmem/snvs-lpgpr.yaml#
17 - fsl,imx8mm-snvs-lpgpr
18 - fsl,imx8mn-snvs-lpgpr
19 - fsl,imx8mp-snvs-lpgpr
20 - fsl,imx8mq-snvs-lpgpr
21 - const: fsl,imx7d-snvs-lpgpr
23 - fsl,imx6q-snvs-lpgpr
24 - fsl,imx6ul-snvs-lpgpr
25 - fsl,imx7d-snvs-lpgpr
34 snvs@20cc000 {
[all …]
/linux/Documentation/devicetree/bindings/mfd/
H A Drohm,bd71847-pmic.yaml45 # states. States are called as SNVS and READY. At READY state all the PMIC
46 # power outputs go down and OTP is reload. At the SNVS state all other logic
47 # and external devices apart from the SNVS power domain are shut off. Please
48 # refer to NXP i.MX8 documentation for further information regarding SNVS
49 # state. When a reset is done via SNVS state the PMIC OTP data is not reload.
51 # reset has switched power state to SNVS. If reset is done via READY state the
53 # target state is set to READY by default. If SNVS state is used the boot
57 rohm,reset-snvs-powered:
59 Transfer PMIC to SNVS state at reset.
144 rohm,reset-snvs-powered;
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ull-dhcom-som.dtsi588 pinctrl_snvs_dhcom_a: snvs-dhcom-a-grp {
592 pinctrl_snvs_dhcom_b: snvs-dhcom-b-grp {
596 pinctrl_snvs_dhcom_c: snvs-dhcom-c-grp {
600 pinctrl_snvs_dhcom_d: snvs-dhcom-d-grp {
604 pinctrl_snvs_dhcom_e: snvs-dhcom-e-grp {
608 pinctrl_snvs_dhcom_f: snvs-dhcom-f-grp {
612 pinctrl_snvs_dhcom_g: snvs-dhcom-g-grp {
616 pinctrl_snvs_dhcom_h: snvs-dhcom-h-grp {
620 pinctrl_snvs_fec1_phy: snvs-fec1-phy-grp {
626 pinctrl_snvs_fec2_phy: snvs-fec2-phy-grp {
H A Dimx6ull-dhcor-maveo-box.dts334 pinctrl_snvs_hog_maveo_box: snvs-hog-maveo-box-grp {
347 pinctrl_snvs_wifi_gpio: snvs-wifi-gpio-grp {
353 pinctrl_snvs_zigbee_gpio: snvs-zigbee-gpio-grp {
H A Dimx6ull-jozacp.dts439 pinctrl_snvs_hog: snvs-hog-grp {
H A Dimx6qdl-skov-cpu.dtsi22 rtc1 = &snvs;
/linux/drivers/nvmem/
H A Dsnvs_lpgpr.c138 { .compatible = "fsl,imx6q-snvs-lpgpr", .data = &snvs_lpgpr_cfg_imx6q },
139 { .compatible = "fsl,imx6ul-snvs-lpgpr",
141 { .compatible = "fsl,imx7d-snvs-lpgpr", .data = &snvs_lpgpr_cfg_imx7d },
/linux/drivers/rtc/
H A Drtc-snvs.c334 dev_warn(&pdev->dev, "snvs rtc: you use old dts file, please update it\n"); in snvs_rtc_probe()
347 dev_err(&pdev->dev, "Can't find snvs syscon\n"); in snvs_rtc_probe()
355 data->clk = devm_clk_get(&pdev->dev, "snvs-rtc"); in snvs_rtc_probe()
362 "Could not prepare or enable the snvs clock\n"); in snvs_rtc_probe()
445 MODULE_DESCRIPTION("Freescale SNVS RTC Driver");
H A DMakefile176 obj-$(CONFIG_RTC_DRV_SNVS) += rtc-snvs.o
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mn-ddr4-evk.dts60 rohm,reset-snvs-powered;
H A Dimx8mm-ucm-som.dtsi143 rohm,reset-snvs-powered;
309 &snvs {
H A Dimx8mq-nitrogen-som.dtsi24 reg_snvs: regulator-fixed-snvs {
H A Dimx8mq-librem5.dtsi874 rohm,reset-snvs-powered;
952 /* leave on for snvs power button */
961 /* leave on for snvs power button */
H A Dimx8mn-bsh-smm-s2-common.dtsi93 rohm,reset-snvs-powered;
H A Dimx8mm-innocomm-wb15.dtsi73 rohm,reset-snvs-powered;
H A Dimx8mm-beacon-som.dtsi117 rohm,reset-snvs-powered;
H A Dimx8mn-beacon-som.dtsi127 rohm,reset-snvs-powered;
H A Dimx8mm-emcon.dtsi408 rohm,reset-snvs-powered;
H A Dimx8mm-venice-gw7904.dts468 rohm,reset-snvs-powered;
H A Dimx8mm-venice-gw7903.dts421 rohm,reset-snvs-powered;
H A Dimx8mm-data-modul-edm-sbc.dts300 rohm,reset-snvs-powered;
H A Dimx8mn-venice-gw7902.dts435 rohm,reset-snvs-powered;
H A Dimx8mm-venice-gw7901.dts524 rohm,reset-snvs-powered;
/linux/drivers/pinctrl/freescale/
H A Dpinctrl-imx6ul.c327 { .compatible = "fsl,imx6ull-iomuxc-snvs", .data = &imx6ull_snvs_pinctrl_info, },
/linux/drivers/regulator/
H A Dpf9453-regulator.c704 .of_match = of_match_ptr("LDO-SNVS"),

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