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/linux/drivers/gpu/drm/amd/pm/swsmu/
H A Damdgpu_smu.c62 static int smu_force_smuclk_levels(struct smu_context *smu,
65 static int smu_handle_task(struct smu_context *smu,
68 static int smu_reset(struct smu_context *smu);
73 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);
75 static void smu_power_profile_mode_get(struct smu_context *smu,
77 static void smu_power_profile_mode_put(struct smu_context *smu,
87 struct smu_context *smu = handle; in smu_sys_get_pp_feature_mask() local
89 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) in smu_sys_get_pp_feature_mask()
92 return smu_get_pp_feature_mask(smu, buf); in smu_sys_get_pp_feature_mask()
98 struct smu_context *smu = handle; in smu_sys_set_pp_feature_mask() local
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H A Dsmu_cmn.c50 #define smu_cmn_call_asic_func(intf, smu, args...) \ argument
51 ((smu)->ppt_funcs ? ((smu)->ppt_funcs->intf ? \
52 (smu)->ppt_funcs->intf(smu, ##args) : \
56 static const char *smu_get_message_name(struct smu_context *smu, in smu_get_message_name() argument
60 return "unknown smu message"; in smu_get_message_name()
65 static void smu_cmn_read_arg(struct smu_context *smu, in smu_cmn_read_arg() argument
68 struct amdgpu_device *adev = smu->adev; in smu_cmn_read_arg()
70 *arg = RREG32(smu->param_reg); in smu_cmn_read_arg()
73 /* Redefine the SMU error codes here.
76 * when the SMU has exported a unified header file containing these
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H A Dsmu_cmn.h104 int smu_cmn_send_msg_without_waiting(struct smu_context *smu,
107 int smu_cmn_send_smc_msg_with_param(struct smu_context *smu,
112 int smu_cmn_send_smc_msg(struct smu_context *smu,
116 int smu_cmn_send_debug_smc_msg(struct smu_context *smu,
119 int smu_cmn_send_debug_smc_msg_with_param(struct smu_context *smu,
122 int smu_cmn_wait_for_response(struct smu_context *smu);
124 int smu_cmn_to_asic_specific_index(struct smu_context *smu,
128 int smu_cmn_feature_is_supported(struct smu_context *smu,
131 int smu_cmn_feature_is_enabled(struct smu_context *smu,
134 bool smu_cmn_clk_dpm_is_enabled(struct smu_context *smu,
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/linux/drivers/gpu/drm/amd/pm/swsmu/smu14/
H A Dsmu_v14_0.c69 int smu_v14_0_init_microcode(struct smu_context *smu) in smu_v14_0_init_microcode() argument
71 struct amdgpu_device *adev = smu->adev; in smu_v14_0_init_microcode()
78 /* doesn't need to load smu firmware in IOV mode */ in smu_v14_0_init_microcode()
111 void smu_v14_0_fini_microcode(struct smu_context *smu) in smu_v14_0_fini_microcode() argument
113 struct amdgpu_device *adev = smu->adev; in smu_v14_0_fini_microcode()
119 int smu_v14_0_load_microcode(struct smu_context *smu) in smu_v14_0_load_microcode() argument
121 struct amdgpu_device *adev = smu->adev; in smu_v14_0_load_microcode()
145 if (smu->is_apu) in smu_v14_0_load_microcode()
163 int smu_v14_0_init_pptable_microcode(struct smu_context *smu) in smu_v14_0_init_pptable_microcode() argument
165 struct amdgpu_device *adev = smu->adev; in smu_v14_0_init_pptable_microcode()
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/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0.c93 int smu_v13_0_init_microcode(struct smu_context *smu) in smu_v13_0_init_microcode() argument
95 struct amdgpu_device *adev = smu->adev; in smu_v13_0_init_microcode()
102 /* doesn't need to load smu firmware in IOV mode */ in smu_v13_0_init_microcode()
136 void smu_v13_0_fini_microcode(struct smu_context *smu) in smu_v13_0_fini_microcode() argument
138 struct amdgpu_device *adev = smu->adev; in smu_v13_0_fini_microcode()
144 int smu_v13_0_load_microcode(struct smu_context *smu) in smu_v13_0_load_microcode() argument
147 struct amdgpu_device *adev = smu->adev; in smu_v13_0_load_microcode()
186 int smu_v13_0_init_pptable_microcode(struct smu_context *smu) in smu_v13_0_init_pptable_microcode() argument
188 struct amdgpu_device *adev = smu->adev; in smu_v13_0_init_pptable_microcode()
194 /* doesn't need to load smu firmware in IOV mode */ in smu_v13_0_init_pptable_microcode()
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H A Dsmu_v13_0_4_ppt.c150 static int smu_v13_0_4_init_smc_tables(struct smu_context *smu) in smu_v13_0_4_init_smc_tables() argument
152 struct smu_table_context *smu_table = &smu->smu_table; in smu_v13_0_4_init_smc_tables()
192 static int smu_v13_0_4_fini_smc_tables(struct smu_context *smu) in smu_v13_0_4_fini_smc_tables() argument
194 struct smu_table_context *smu_table = &smu->smu_table; in smu_v13_0_4_fini_smc_tables()
211 static bool smu_v13_0_4_is_dpm_running(struct smu_context *smu) in smu_v13_0_4_is_dpm_running() argument
216 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); in smu_v13_0_4_is_dpm_running()
224 static int smu_v13_0_4_system_features_control(struct smu_context *smu, bool en) in smu_v13_0_4_system_features_control() argument
226 struct amdgpu_device *adev = smu->adev; in smu_v13_0_4_system_features_control()
235 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, in smu_v13_0_4_system_features_control()
241 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL); in smu_v13_0_4_system_features_control()
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H A Dsmu_v13_0_6_ppt.c258 static inline int smu_v13_0_6_get_metrics_version(struct smu_context *smu) in smu_v13_0_6_get_metrics_version() argument
260 if ((smu->adev->flags & AMD_IS_APU) && in smu_v13_0_6_get_metrics_version()
261 smu->smc_fw_version <= 0x4556900) in smu_v13_0_6_get_metrics_version()
263 else if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == in smu_v13_0_6_get_metrics_version()
270 static inline void smu_v13_0_6_cap_set(struct smu_context *smu, in smu_v13_0_6_cap_set() argument
273 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; in smu_v13_0_6_cap_set()
278 static inline void smu_v13_0_6_cap_clear(struct smu_context *smu, in smu_v13_0_6_cap_clear() argument
281 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; in smu_v13_0_6_cap_clear()
286 bool smu_v13_0_6_cap_supported(struct smu_context *smu, in smu_v13_0_6_cap_supported() argument
289 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; in smu_v13_0_6_cap_supported()
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/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dsmu_v11_0.c82 static void smu_v11_0_poll_baco_exit(struct smu_context *smu) in smu_v11_0_poll_baco_exit() argument
84 struct amdgpu_device *adev = smu->adev; in smu_v11_0_poll_baco_exit()
93 int smu_v11_0_init_microcode(struct smu_context *smu) in smu_v11_0_init_microcode() argument
95 struct amdgpu_device *adev = smu->adev; in smu_v11_0_init_microcode()
132 void smu_v11_0_fini_microcode(struct smu_context *smu) in smu_v11_0_fini_microcode() argument
134 struct amdgpu_device *adev = smu->adev; in smu_v11_0_fini_microcode()
140 int smu_v11_0_load_microcode(struct smu_context *smu) in smu_v11_0_load_microcode() argument
142 struct amdgpu_device *adev = smu->adev; in smu_v11_0_load_microcode()
180 int smu_v11_0_check_fw_status(struct smu_context *smu) in smu_v11_0_check_fw_status() argument
182 struct amdgpu_device *adev = smu->adev; in smu_v11_0_check_fw_status()
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H A Dcyan_skillfish_ppt.c87 static int cyan_skillfish_tables_init(struct smu_context *smu) in cyan_skillfish_tables_init() argument
89 struct smu_table_context *smu_table = &smu->smu_table; in cyan_skillfish_tables_init()
117 static int cyan_skillfish_init_smc_tables(struct smu_context *smu) in cyan_skillfish_init_smc_tables() argument
121 ret = cyan_skillfish_tables_init(smu); in cyan_skillfish_init_smc_tables()
125 return smu_v11_0_init_smc_tables(smu); in cyan_skillfish_init_smc_tables()
129 cyan_skillfish_get_smu_metrics_data(struct smu_context *smu, in cyan_skillfish_get_smu_metrics_data() argument
133 struct smu_table_context *smu_table = &smu->smu_table; in cyan_skillfish_get_smu_metrics_data()
137 ret = smu_cmn_get_metrics_table(smu, NULL, false); in cyan_skillfish_get_smu_metrics_data()
190 static int cyan_skillfish_read_sensor(struct smu_context *smu, in cyan_skillfish_read_sensor() argument
202 ret = cyan_skillfish_get_smu_metrics_data(smu, in cyan_skillfish_read_sensor()
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/linux/arch/powerpc/include/asm/
H A Dsmu.h6 * Definitions for talking to the SMU chip in newer G5 PowerMacs
14 * Known SMU commands
26 * the SMU. The length is always 2. First byte is the subcommand code
87 * The "RTC" part of the SMU controls the date, time, powerup
112 * the SMU. This is a command of type 0x9a with 9 bytes of header
115 * 0: bus number (from device-tree usually, SMU has lots of busses !)
137 * or if this is an SMU imposed limit. This driver has the same limitation
140 * Once that is completed, a response is expected from the SMU. This is
183 * used to set the voltage slewing point. The SMU replies with "DONE"
248 * frequency) depends on current time. Therefore, the SMU needs to know the
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/linux/drivers/macintosh/
H A Dwindfarm_smu_controls.c3 * Windfarm PowerMac thermal control. SMU based controls
22 #include <asm/smu.h>
39 * SMU fans control object
47 u32 reg; /* index in SMU */
61 /* Fill SMU command structure */ in smu_set_fan()
64 /* The SMU has an "old" and a "new" way of setting the fan speed in smu_set_fan()
100 printk(KERN_WARNING "windfarm: SMU failed new fan command " in smu_set_fan()
132 *value = fct->value; /* todo: read from SMU */ in smu_fan_get()
176 /* We use the name & location here the same way we do for SMU sensors, in smu_fan_create()
259 struct device_node *smu, *fans, *fan; in smu_controls_init() local
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H A Dwindfarm_smu_sensors.c3 * Windfarm PowerMac thermal control. SMU based sensors
22 #include <asm/smu.h>
37 * Various SMU "partitions" calibration objects for which we
47 * SMU basic sensors objects
54 u32 reg; /* index in SMU */
270 * SMU Power combo sensor object
411 struct device_node *smu, *sensors, *s; in smu_sensors_init() local
420 smu = of_find_node_by_type(NULL, "smu"); in smu_sensors_init()
421 if (smu == NULL) in smu_sensors_init()
425 for_each_child_of_node(smu, sensors) in smu_sensors_init()
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/linux/Documentation/devicetree/bindings/clock/
H A Drenesas,emev2-smu.yaml4 $id: http://devicetree.org/schemas/clock/renesas,emev2-smu.yaml#
15 This is not a clock provider, but clocks under SMU depend on it.
19 const: renesas,emev2-smu
49 const: renesas,emev2-smu-clkdiv
54 Byte offset from SMU base and Bit position in the register.
81 const: renesas,emev2-smu-gclk
86 Byte offset from SMU base and Bit position in the register.
111 compatible = "renesas,emev2-smu";
129 compatible = "renesas,emev2-smu-clkdiv";
135 compatible = "renesas,emev2-smu-gclk";
/linux/arch/arm/boot/dts/renesas/
H A Demev2.dtsi61 compatible = "renesas,emev2-smu";
72 compatible = "renesas,emev2-smu-clkdiv";
78 compatible = "renesas,emev2-smu-gclk";
84 compatible = "renesas,emev2-smu-clkdiv";
90 compatible = "renesas,emev2-smu-gclk";
103 compatible = "renesas,emev2-smu-clkdiv";
109 compatible = "renesas,emev2-smu-clkdiv";
115 compatible = "renesas,emev2-smu-clkdiv";
121 compatible = "renesas,emev2-smu-clkdiv";
127 compatible = "renesas,emev2-smu-gclk";
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/linux/arch/arm/mach-shmobile/
H A Dsmp-emev2.c32 void __iomem *smu; in emev2_smp_prepare_cpus() local
35 smu = ioremap(EMEV2_SMU_BASE, PAGE_SIZE); in emev2_smp_prepare_cpus()
36 if (smu) { in emev2_smp_prepare_cpus()
37 iowrite32(__pa(shmobile_boot_vector), smu + SMU_GENERAL_REG0); in emev2_smp_prepare_cpus()
38 iounmap(smu); in emev2_smp_prepare_cpus()
/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dvega20_smumgr.c172 "Invalid SMU Table ID!", return -EINVAL); in vega20_copy_table_from_smc()
174 "Invalid SMU Table version!", return -EINVAL); in vega20_copy_table_from_smc()
176 "Invalid SMU Table Length!", return -EINVAL); in vega20_copy_table_from_smc()
192 "[CopyTableFromSMC] Attempt to Transfer Table From SMU Failed!", in vega20_copy_table_from_smc()
217 "Invalid SMU Table ID!", return -EINVAL); in vega20_copy_table_to_smc()
219 "Invalid SMU Table version!", return -EINVAL); in vega20_copy_table_to_smc()
221 "Invalid SMU Table Length!", return -EINVAL); in vega20_copy_table_to_smc()
242 "[CopyTableToSMC] Attempt to Transfer Table To SMU Failed!", in vega20_copy_table_to_smc()
277 "[SetActivityMonitor] Attempt to Transfer Table To SMU Failed!", in vega20_set_activity_monitor_coeff()
306 "[GetActivityMonitor] Attempt to Transfer Table From SMU Failed!", in vega20_get_activity_monitor_coeff()
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H A Dvega10_smumgr.c45 "Invalid SMU Table ID!", return -EINVAL); in vega10_copy_table_from_smc()
47 "Invalid SMU Table version!", return -EINVAL); in vega10_copy_table_from_smc()
49 "Invalid SMU Table Length!", return -EINVAL); in vega10_copy_table_from_smc()
84 "Invalid SMU Table ID!", return -EINVAL); in vega10_copy_table_to_smc()
86 "Invalid SMU Table version!", return -EINVAL); in vega10_copy_table_to_smc()
88 "Invalid SMU Table Length!", return -EINVAL); in vega10_copy_table_to_smc()
117 /* VF has no permission to change smu feature due in vega10_enable_smc_features()
119 * it still can't do it. For vega10, the smu in in vega10_enable_smc_features()
H A Dsmu10_smumgr.c124 "Invalid SMU Table ID!", return -EINVAL;); in smu10_copy_table_from_smc()
126 "Invalid SMU Table version!", return -EINVAL;); in smu10_copy_table_from_smc()
128 "Invalid SMU Table Length!", return -EINVAL;); in smu10_copy_table_from_smc()
158 "Invalid SMU Table ID!", return -EINVAL;); in smu10_copy_table_to_smc()
160 "Invalid SMU Table version!", return -EINVAL;); in smu10_copy_table_to_smc()
162 "Invalid SMU Table Length!", return -EINVAL;); in smu10_copy_table_to_smc()
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu11_driver_if_navi10.h27 // SMU TEAM: Always increment the interface version if
320 uint32_t MmHubPadding[8]; // SMU internal use
561 …uint8_t GceaLinkMgrIdleThreshold; //Set by SMU FW during enablment of SOC_ULV. Controls d…
733 …uint16_t MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple step…
734 …uint16_t MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple step…
815 uint32_t MmHubPadding[8]; // SMU internal use
830 uint32_t MmHubPadding[8]; // SMU internal use
856 uint32_t MmHubPadding[6]; // SMU internal use
890 uint32_t MmHubPadding[8]; // SMU internal use
929 uint32_t MmHubPadding[8]; // SMU internal use
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/linux/drivers/platform/x86/amd/pmc/
H A Dpmc.c137 dev_warn_once(dev->dev, "SMU debugging info not supported on this platform\n"); in amd_pmc_setup_smu_logging()
141 /* Get Active devices list from SMU */ in amd_pmc_setup_smu_logging()
215 dev_dbg(dev->dev, "SMU program %u version is %u.%u.%u\n", in amd_pmc_get_smu_version()
287 seq_puts(s, "\n=== SMU Statistics ===\n"); in smu_fw_info_show()
351 /* we haven't yet read SMU version */ in amd_pmc_idlemask_read()
376 pm_pr_dbg("SMU idlemask s0i3: 0x%x\n", val); in amd_pmc_idlemask_read()
379 seq_printf(s, "SMU idlemask : 0x%x\n", val); in amd_pmc_idlemask_read()
464 dev_err(dev->dev, "failed to talk to SMU\n"); in amd_pmc_send_cmd()
482 dev_err(dev->dev, "SMU response timed out\n"); in amd_pmc_send_cmd()
495 dev_err(dev->dev, "SMU not ready. err: 0x%x\n", val); in amd_pmc_send_cmd()
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/linux/drivers/clk/renesas/
H A Dclk-emev2.c13 /* EMEV2 SMU registers */
35 { .compatible = "renesas,emev2-smu", },
78 CLK_OF_DECLARE(emev2_smu_clkdiv, "renesas,emev2-smu-clkdiv",
95 CLK_OF_DECLARE(emev2_smu_gclk, "renesas,emev2-smu-gclk", emev2_smu_gclk_init);
/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dsmu9_driver_if.h30 * SMU TEAM: Always increment the interface version if
173 …uint8_t MaxVidStep; /* Max VID step that SMU will request. Multiple steps are taken if voltag…
324 uint32_t MmHubPadding[3]; /* SMU internal use */
351 uint32_t MmHubPadding[7]; /* SMU internal use */
362 uint32_t MmHubPadding[7]; /* SMU internal use */
372 uint32_t MmHubPadding[7]; /* SMU internal use */
382 uint32_t MmHubPadding[7]; /* SMU internal use */
424 uint32_t MmHubPadding[7]; /* SMU internal use */
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_smu.c112 smu_print("SMU Response was not OK. SMU response after wait received is: %d\n", result); in dcn31_smu_send_msg_with_param()
121 /* Set the parameter register for the SMU message, unit is Mhz */ in dcn31_smu_send_msg_with_param()
132 DC_LOG_DEBUG("Watermarks table not configured properly by SMU"); in dcn31_smu_send_msg_with_param()
163 /* Unit of SMU msg parameter is Mhz */ in dcn31_smu_set_dispclk()
248 //TODO: Work with smu team to define optimization options. in dcn31_smu_set_display_idle_optimization()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Ddcn301_smu.c107 smu_print("SMU Response was not OK. SMU response after wait received is: %d\n", result); in dcn301_smu_send_msg_with_param()
116 /* Set the parameter register for the SMU message, unit is Mhz */ in dcn301_smu_send_msg_with_param()
151 /* Unit of SMU msg parameter is Mhz */ in dcn301_smu_set_dispclk()
220 //TODO: Work with smu team to define optimization options. in dcn301_smu_set_display_idle_optimization()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_smu.c128 smu_print("SMU Response was not OK. SMU response after wait received is: %d\n", in dcn314_smu_send_msg_with_param()
137 /* Set the parameter register for the SMU message, unit is Mhz */ in dcn314_smu_send_msg_with_param()
148 DC_LOG_DEBUG("Watermarks table not configured properly by SMU"); in dcn314_smu_send_msg_with_param()
182 /* Unit of SMU msg parameter is Mhz */ in dcn314_smu_set_dispclk()
267 //TODO: Work with smu team to define optimization options. in dcn314_smu_set_display_idle_optimization()

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