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/linux/drivers/gpu/drm/amd/pm/swsmu/
H A Damdgpu_smu.c62 static int smu_force_smuclk_levels(struct smu_context *smu,
65 static int smu_handle_task(struct smu_context *smu,
68 static int smu_reset(struct smu_context *smu);
73 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);
75 static void smu_power_profile_mode_get(struct smu_context *smu,
77 static void smu_power_profile_mode_put(struct smu_context *smu,
83 struct smu_context *smu = handle; in smu_sys_get_pp_feature_mask() local
85 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) in smu_sys_get_pp_feature_mask()
88 return smu_get_pp_feature_mask(smu, buf); in smu_sys_get_pp_feature_mask()
94 struct smu_context *smu = handle; in smu_sys_set_pp_feature_mask() local
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/linux/drivers/gpu/drm/amd/pm/swsmu/inc/
H A Dsmu_v13_0.h129 int smu_v13_0_init_microcode(struct smu_context *smu);
131 void smu_v13_0_fini_microcode(struct smu_context *smu);
133 int smu_v13_0_load_microcode(struct smu_context *smu);
135 int smu_v13_0_init_smc_tables(struct smu_context *smu);
137 int smu_v13_0_fini_smc_tables(struct smu_context *smu);
139 int smu_v13_0_init_power(struct smu_context *smu);
141 int smu_v13_0_fini_power(struct smu_context *smu);
143 int smu_v13_0_check_fw_status(struct smu_context *smu);
145 int smu_v13_0_setup_pptable(struct smu_context *smu);
147 int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu);
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/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0.c92 int smu_v13_0_init_microcode(struct smu_context *smu) in smu_v13_0_init_microcode() argument
94 struct amdgpu_device *adev = smu->adev; in smu_v13_0_init_microcode()
101 /* doesn't need to load smu firmware in IOV mode */ in smu_v13_0_init_microcode()
129 void smu_v13_0_fini_microcode(struct smu_context *smu) in smu_v13_0_fini_microcode() argument
131 struct amdgpu_device *adev = smu->adev; in smu_v13_0_fini_microcode()
137 int smu_v13_0_load_microcode(struct smu_context *smu) in smu_v13_0_load_microcode() argument
140 struct amdgpu_device *adev = smu->adev; in smu_v13_0_load_microcode()
179 int smu_v13_0_init_pptable_microcode(struct smu_context *smu) in smu_v13_0_init_pptable_microcode() argument
181 struct amdgpu_device *adev = smu->adev; in smu_v13_0_init_pptable_microcode()
187 /* doesn't need to load smu firmware in IOV mode */ in smu_v13_0_init_pptable_microcode()
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H A Dsmu_v13_0_4_ppt.c150 static int smu_v13_0_4_init_smc_tables(struct smu_context *smu) in smu_v13_0_4_init_smc_tables() argument
152 struct smu_table_context *smu_table = &smu->smu_table; in smu_v13_0_4_init_smc_tables()
192 static int smu_v13_0_4_fini_smc_tables(struct smu_context *smu) in smu_v13_0_4_fini_smc_tables() argument
194 struct smu_table_context *smu_table = &smu->smu_table; in smu_v13_0_4_fini_smc_tables()
211 static bool smu_v13_0_4_is_dpm_running(struct smu_context *smu) in smu_v13_0_4_is_dpm_running() argument
216 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); in smu_v13_0_4_is_dpm_running()
224 static int smu_v13_0_4_system_features_control(struct smu_context *smu, bool en) in smu_v13_0_4_system_features_control() argument
226 struct amdgpu_device *adev = smu->adev; in smu_v13_0_4_system_features_control()
235 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, in smu_v13_0_4_system_features_control()
241 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL); in smu_v13_0_4_system_features_control()
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H A Dsmu_v13_0_0_ppt.c299 smu_v13_0_0_get_allowed_feature_mask(struct smu_context *smu, in smu_v13_0_0_get_allowed_feature_mask() argument
302 struct amdgpu_device *adev = smu->adev; in smu_v13_0_0_get_allowed_feature_mask()
322 if ((smu->smc_fw_version < 0x004e3a00) || in smu_v13_0_0_get_allowed_feature_mask()
346 static int smu_v13_0_0_check_powerplay_table(struct smu_context *smu) in smu_v13_0_0_check_powerplay_table() argument
348 struct smu_table_context *table_context = &smu->smu_table; in smu_v13_0_0_check_powerplay_table()
351 struct smu_baco_context *smu_baco = &smu->smu_baco; in smu_v13_0_0_check_powerplay_table()
352 PPTable_t *pptable = smu->smu_table.driver_pptable; in smu_v13_0_0_check_powerplay_table()
359 smu->dc_controlled_by_gpio = true; in smu_v13_0_0_check_powerplay_table()
370 smu->od_enabled = false; in smu_v13_0_0_check_powerplay_table()
377 * smu->od_settings just points to the actual overdrive_table in smu_v13_0_0_check_powerplay_table()
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H A Dsmu_v13_0_7_ppt.c268 smu_v13_0_7_get_allowed_feature_mask(struct smu_context *smu, in smu_v13_0_7_get_allowed_feature_mask() argument
271 struct amdgpu_device *adev = smu->adev; in smu_v13_0_7_get_allowed_feature_mask()
337 static int smu_v13_0_7_check_powerplay_table(struct smu_context *smu) in smu_v13_0_7_check_powerplay_table() argument
339 struct smu_table_context *table_context = &smu->smu_table; in smu_v13_0_7_check_powerplay_table()
342 struct smu_baco_context *smu_baco = &smu->smu_baco; in smu_v13_0_7_check_powerplay_table()
351 smu->dc_controlled_by_gpio = true; in smu_v13_0_7_check_powerplay_table()
363 smu->od_enabled = false; in smu_v13_0_7_check_powerplay_table()
370 * smu->od_settings just points to the actual overdrive_table in smu_v13_0_7_check_powerplay_table()
372 smu->od_settings = &powerplay_table->overdrive_table; in smu_v13_0_7_check_powerplay_table()
377 static int smu_v13_0_7_store_powerplay_table(struct smu_context *smu) in smu_v13_0_7_store_powerplay_table() argument
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/linux/drivers/gpu/drm/amd/pm/swsmu/smu14/
H A Dsmu_v14_0_0_ppt.c185 static int smu_v14_0_0_init_smc_tables(struct smu_context *smu) in smu_v14_0_0_init_smc_tables() argument
187 struct smu_table_context *smu_table = &smu->smu_table; in smu_v14_0_0_init_smc_tables()
227 static int smu_v14_0_0_fini_smc_tables(struct smu_context *smu) in smu_v14_0_0_fini_smc_tables() argument
229 struct smu_table_context *smu_table = &smu->smu_table; in smu_v14_0_0_fini_smc_tables()
246 static int smu_v14_0_0_system_features_control(struct smu_context *smu, bool en) in smu_v14_0_0_system_features_control() argument
248 struct amdgpu_device *adev = smu->adev; in smu_v14_0_0_system_features_control()
252 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL); in smu_v14_0_0_system_features_control()
257 static int smu_v14_0_0_get_smu_metrics_data(struct smu_context *smu, in smu_v14_0_0_get_smu_metrics_data() argument
261 struct smu_table_context *smu_table = &smu->smu_table; in smu_v14_0_0_get_smu_metrics_data()
266 ret = smu_cmn_get_metrics_table(smu, NULL, false); in smu_v14_0_0_get_smu_metrics_data()
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H A Dsmu_v14_0_2_ppt.c267 smu_v14_0_2_get_allowed_feature_mask(struct smu_context *smu, in smu_v14_0_2_get_allowed_feature_mask() argument
270 struct amdgpu_device *adev = smu->adev; in smu_v14_0_2_get_allowed_feature_mask()
291 smu_cmn_get_smc_version(smu, NULL, &smu_version); in smu_v14_0_2_get_allowed_feature_mask()
317 static int smu_v14_0_2_check_powerplay_table(struct smu_context *smu) in smu_v14_0_2_check_powerplay_table() argument
319 struct smu_table_context *table_context = &smu->smu_table; in smu_v14_0_2_check_powerplay_table()
322 struct smu_baco_context *smu_baco = &smu->smu_baco; in smu_v14_0_2_check_powerplay_table()
323 PPTable_t *pptable = smu->smu_table.driver_pptable; in smu_v14_0_2_check_powerplay_table()
330 smu->dc_controlled_by_gpio = true; in smu_v14_0_2_check_powerplay_table()
341 smu->od_enabled = false; in smu_v14_0_2_check_powerplay_table()
348 * smu->od_settings just points to the actual overdrive_table in smu_v14_0_2_check_powerplay_table()
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/linux/drivers/macintosh/
H A Dsmu.c3 * PowerMac G5 SMU driver
15 * - maybe avoid some data copies with i2c by directly using the smu cmd
17 * - understand SMU -> CPU events and implement reception of them via
48 #include <asm/smu.h>
64 * This is the command buffer passed to the SMU hardware
96 * I don't think there will ever be more than one SMU, so
100 static struct smu_device *smu; variable
108 * SMU driver low level stuff
116 if (list_empty(&smu->cmd_list)) in smu_start_cmd()
120 cmd = list_entry(smu->cmd_list.next, struct smu_cmd, link); in smu_start_cmd()
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H A Dwindfarm_smu_controls.c3 * Windfarm PowerMac thermal control. SMU based controls
22 #include <asm/smu.h>
39 * SMU fans control object
47 u32 reg; /* index in SMU */
61 /* Fill SMU command structure */ in smu_set_fan()
64 /* The SMU has an "old" and a "new" way of setting the fan speed in smu_set_fan()
100 printk(KERN_WARNING "windfarm: SMU failed new fan command " in smu_set_fan()
132 *value = fct->value; /* todo: read from SMU */ in smu_fan_get()
176 /* We use the name & location here the same way we do for SMU sensors, in smu_fan_create()
259 struct device_node *smu, *fans, *fan; in smu_controls_init() local
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H A Dwindfarm_smu_sensors.c3 * Windfarm PowerMac thermal control. SMU based sensors
22 #include <asm/smu.h>
37 * Various SMU "partitions" calibration objects for which we
47 * SMU basic sensors objects
54 u32 reg; /* index in SMU */
270 * SMU Power combo sensor object
411 struct device_node *smu, *sensors, *s; in smu_sensors_init() local
420 smu = of_find_node_by_type(NULL, "smu"); in smu_sensors_init()
421 if (smu == NULL) in smu_sensors_init()
425 for_each_child_of_node(smu, sensors) in smu_sensors_init()
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/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dcyan_skillfish_ppt.c87 static int cyan_skillfish_tables_init(struct smu_context *smu) in cyan_skillfish_tables_init() argument
89 struct smu_table_context *smu_table = &smu->smu_table; in cyan_skillfish_tables_init()
117 static int cyan_skillfish_init_smc_tables(struct smu_context *smu) in cyan_skillfish_init_smc_tables() argument
121 ret = cyan_skillfish_tables_init(smu); in cyan_skillfish_init_smc_tables()
125 return smu_v11_0_init_smc_tables(smu); in cyan_skillfish_init_smc_tables()
129 cyan_skillfish_get_smu_metrics_data(struct smu_context *smu, in cyan_skillfish_get_smu_metrics_data() argument
133 struct smu_table_context *smu_table = &smu->smu_table; in cyan_skillfish_get_smu_metrics_data()
137 ret = smu_cmn_get_metrics_table(smu, NULL, false); in cyan_skillfish_get_smu_metrics_data()
190 static int cyan_skillfish_read_sensor(struct smu_context *smu, in cyan_skillfish_read_sensor() argument
202 ret = cyan_skillfish_get_smu_metrics_data(smu, in cyan_skillfish_read_sensor()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddcn30_clk_mgr_smu_msg.c86 /* Set the parameter register for the SMU message */ in dcn30_smu_send_msg_with_param()
116 smu_print("SMU Test message: %d\n", input); in dcn30_smu_test_message()
128 smu_print("SMU Get SMU version\n"); in dcn30_smu_get_smu_version()
133 smu_print("SMU version: %d\n", *version); in dcn30_smu_get_smu_version()
146 smu_print("SMU Check driver if version\n"); in dcn30_smu_check_driver_if_version()
151 smu_print("SMU driver if version: %d\n", response); in dcn30_smu_check_driver_if_version()
165 smu_print("SMU Check msg header version\n"); in dcn30_smu_check_msg_header_version()
170 smu_print("SMU msg header version: %d\n", response); in dcn30_smu_check_msg_header_version()
181 smu_print("SMU Set DRAM addr high: %d\n", addr_high); in dcn30_smu_set_dram_addr_high()
189 smu_print("SMU Set DRAM addr low: %d\n", addr_low); in dcn30_smu_set_dram_addr_low()
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/linux/arch/powerpc/include/asm/
H A Dsmu.h6 * Definitions for talking to the SMU chip in newer G5 PowerMacs
14 * Known SMU commands
26 * the SMU. The length is always 2. First byte is the subcommand code
87 * The "RTC" part of the SMU controls the date, time, powerup
112 * the SMU. This is a command of type 0x9a with 9 bytes of header
115 * 0: bus number (from device-tree usually, SMU has lots of busses !)
137 * or if this is an SMU imposed limit. This driver has the same limitation
140 * Once that is completed, a response is expected from the SMU. This is
183 * used to set the voltage slewing point. The SMU replies with "DONE"
248 * frequency) depends on current time. Therefore, the SMU needs to know the
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/
H A Ddcn401_clk_mgr_smu_msg.c55 /* Set the parameter register for the SMU message */ in dcn401_smu_send_msg_with_param()
113 /* Set the parameter register for the SMU message */ in dcn401_smu_send_msg_with_param_delay()
160 smu_print("SMU Transfer WM table DRAM 2 SMU\n"); in dcn401_smu_transfer_wm_table_dram_2_smu()
168 smu_print("SMU Set PME workaround\n"); in dcn401_smu_set_pme_workaround()
184 smu_print("SMU Get hard min status: no_timeout %d delay %d us clk bits %x\n", in dcn401_smu_get_hard_min_status()
208 smu_print("SMU Wait hard min status for %d us\n", total_delay_us); in dcn401_smu_wait_hard_min_status()
228 smu_print("SMU Set hard min by freq: clk = %d, freq_mhz = %d MHz\n", clk, freq_mhz); in dcn401_smu_set_hard_min_by_freq()
235 smu_print("SMU Frequency set = %d KHz hard_min_done %d\n", response, hard_min_done); in dcn401_smu_set_hard_min_by_freq()
242 smu_print("SMU to wait for DMCUB ack for MCLK : %d\n", enable); in dcn401_smu_wait_for_dmub_ack_mclk()
249 smu_print("SMU Set indicate drr status = %d\n", mod_drr_for_pstate); in dcn401_smu_indicate_drr_status()
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/linux/Documentation/devicetree/bindings/clock/
H A Drenesas,emev2-smu.yaml4 $id: http://devicetree.org/schemas/clock/renesas,emev2-smu.yaml#
15 This is not a clock provider, but clocks under SMU depend on it.
19 const: renesas,emev2-smu
49 const: renesas,emev2-smu-clkdiv
54 Byte offset from SMU base and Bit position in the register.
81 const: renesas,emev2-smu-gclk
86 Byte offset from SMU base and Bit position in the register.
111 compatible = "renesas,emev2-smu";
129 compatible = "renesas,emev2-smu-clkdiv";
135 compatible = "renesas,emev2-smu-gclk";
/linux/arch/arm/boot/dts/renesas/
H A Demev2.dtsi61 compatible = "renesas,emev2-smu";
72 compatible = "renesas,emev2-smu-clkdiv";
78 compatible = "renesas,emev2-smu-gclk";
84 compatible = "renesas,emev2-smu-clkdiv";
90 compatible = "renesas,emev2-smu-gclk";
103 compatible = "renesas,emev2-smu-clkdiv";
109 compatible = "renesas,emev2-smu-clkdiv";
115 compatible = "renesas,emev2-smu-clkdiv";
121 compatible = "renesas,emev2-smu-clkdiv";
127 compatible = "renesas,emev2-smu-gclk";
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/linux/drivers/mtd/nand/raw/atmel/
H A Dpmecc.c175 s16 *smu; member
356 /* Reserve space for partial_syn, si and smu */ in atmel_pmecc_create_user()
374 user->smu = user->lmu + (req->ecc.strength + 1); in atmel_pmecc_create_user()
375 user->mu = (s32 *)PTR_ALIGN(user->smu + in atmel_pmecc_create_user()
494 s16 *smu = user->smu; in atmel_pmecc_get_sigma() local
508 memset(smu, 0, sizeof(s16) * num); in atmel_pmecc_get_sigma()
509 smu[0] = 1; in atmel_pmecc_get_sigma()
522 memset(&smu[num], 0, sizeof(s16) * num); in atmel_pmecc_get_sigma()
523 smu[num] = 1; in atmel_pmecc_get_sigma()
534 memset(&smu[(strength + 1) * num], 0, sizeof(s16) * num); in atmel_pmecc_get_sigma()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_clk_mgr_smu_msg.c79 /* Set the parameter register for the SMU message */ in dcn32_smu_send_msg_with_param()
139 /* Set the parameter register for the SMU message */ in dcn32_smu_send_msg_with_param_delay()
178 smu_print("SMU Transfer WM table DRAM 2 SMU\n"); in dcn32_smu_transfer_wm_table_dram_2_smu()
186 smu_print("SMU Set PME workaround\n"); in dcn32_smu_set_pme_workaround()
219 smu_print("SMU Get hard min status: no_timeout %d delay %d us clk bits %x\n", in dcn32_smu_get_hard_min_status()
263 smu_print("SMU Wait get hard min status: %d timeouts\n", cur_wait_get_hard_min_max_timeouts); in dcn32_smu_wait_get_hard_min_status()
273 …smu_print("SMU Wait get hard min status: no_timeout %d, delay %d us, max %d us, read %x, check %x\… in dcn32_smu_wait_get_hard_min_status()
288 smu_print("SMU Set hard min by freq: clk = %d, freq_mhz = %d MHz\n", clk, freq_mhz); in dcn32_smu_set_hard_min_by_freq()
295 smu_print("SMU Frequency set = %d KHz hard_min_done %d\n", response, hard_min_done); in dcn32_smu_set_hard_min_by_freq()
297 smu_print("SMU Frequency set = %d KHz\n", response); in dcn32_smu_set_hard_min_by_freq()
/linux/drivers/gpu/drm/amd/pm/
H A Damdgpu_dpm.c115 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_set_gfx_power_up_by_imu() local
119 ret = smu_set_gfx_power_up_by_imu(smu); in amdgpu_dpm_set_gfx_power_up_by_imu()
172 /* VF lost access to SMU */ in amdgpu_dpm_set_mp1_state()
297 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_is_mode1_reset_supported() local
302 support_mode1_reset = smu_mode1_reset_is_support(smu); in amdgpu_dpm_is_mode1_reset_supported()
311 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_mode1_reset() local
316 ret = smu_mode1_reset(smu); in amdgpu_dpm_mode1_reset()
378 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_get_pm_policy_info() local
383 ret = smu_get_pm_policy_info(smu, p_type, buf); in amdgpu_dpm_get_pm_policy_info()
393 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_set_pm_policy() local
[all …]
/linux/arch/arm/mach-shmobile/
H A Dsmp-emev2.c32 void __iomem *smu; in emev2_smp_prepare_cpus() local
35 smu = ioremap(EMEV2_SMU_BASE, PAGE_SIZE); in emev2_smp_prepare_cpus()
36 if (smu) { in emev2_smp_prepare_cpus()
37 iowrite32(__pa(shmobile_boot_vector), smu + SMU_GENERAL_REG0); in emev2_smp_prepare_cpus()
38 iounmap(smu); in emev2_smp_prepare_cpus()
/linux/Documentation/devicetree/bindings/mmc/
H A Dsamsung,exynos-dw-mshc.yaml24 - samsung,exynos5420-dw-mshc-smu
26 - samsung,exynos7-dw-mshc-smu
29 - samsung,exynos5433-dw-mshc-smu
30 - samsung,exynos7885-dw-mshc-smu
31 - samsung,exynos850-dw-mshc-smu
32 - const: samsung,exynos7-dw-mshc-smu
131 - samsung,exynos7-dw-mshc-smu
/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dvega20_smumgr.c172 "Invalid SMU Table ID!", return -EINVAL); in vega20_copy_table_from_smc()
174 "Invalid SMU Table version!", return -EINVAL); in vega20_copy_table_from_smc()
176 "Invalid SMU Table Length!", return -EINVAL); in vega20_copy_table_from_smc()
192 "[CopyTableFromSMC] Attempt to Transfer Table From SMU Failed!", in vega20_copy_table_from_smc()
217 "Invalid SMU Table ID!", return -EINVAL); in vega20_copy_table_to_smc()
219 "Invalid SMU Table version!", return -EINVAL); in vega20_copy_table_to_smc()
221 "Invalid SMU Table Length!", return -EINVAL); in vega20_copy_table_to_smc()
242 "[CopyTableToSMC] Attempt to Transfer Table To SMU Failed!", in vega20_copy_table_to_smc()
277 "[SetActivityMonitor] Attempt to Transfer Table To SMU Failed!", in vega20_set_activity_monitor_coeff()
306 "[GetActivityMonitor] Attempt to Transfer Table From SMU Failed!", in vega20_get_activity_monitor_coeff()
[all …]
/linux/drivers/platform/x86/amd/pmc/
H A Dpmc.c33 /* SMU communication registers */
62 /* Base address of SMU for mapping physical address to virtual address */
70 /* SMU Response Codes */
86 /* SMU Message Definations */
271 /* Spill to DRAM num_samples uses separate SMU message port */ in amd_pmc_stb_debugfs_open_v2()
288 /* Clear msg_port for other SMU operation */ in amd_pmc_stb_debugfs_open_v2()
373 dev_warn_once(dev->dev, "SMU debugging info not supported on this platform\n"); in amd_pmc_setup_smu_logging()
377 /* Get Active devices list from SMU */ in amd_pmc_setup_smu_logging()
448 dev_dbg(dev->dev, "SMU program %u version is %u.%u.%u\n", in amd_pmc_get_smu_version()
520 seq_puts(s, "\n=== SMU Statistics ===\n"); in smu_fw_info_show()
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/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu11_driver_if_navi10.h27 // SMU TEAM: Always increment the interface version if
320 uint32_t MmHubPadding[8]; // SMU internal use
561 …uint8_t GceaLinkMgrIdleThreshold; //Set by SMU FW during enablment of SOC_ULV. Controls d…
733 …uint16_t MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple step…
734 …uint16_t MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple step…
815 uint32_t MmHubPadding[8]; // SMU internal use
830 uint32_t MmHubPadding[8]; // SMU internal use
856 uint32_t MmHubPadding[6]; // SMU internal use
890 uint32_t MmHubPadding[8]; // SMU internal use
929 uint32_t MmHubPadding[8]; // SMU internal use
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