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/linux/Documentation/devicetree/bindings/iommu/
H A Darm,smmu.yaml4 $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
18 The SMMU may also raise interrupts in response to various fault
26 - description: Qcom SoCs implementing "arm,smmu-v2"
29 - qcom,msm8996-smmu-v2
30 - qcom,msm8998-smmu-v2
31 - qcom,sdm630-smmu-v2
32 - qcom,sm6375-smmu-v2
33 - const: qcom,smmu-v2
35 - description: Qcom SoCs implementing "qcom,smmu-500" and "arm,mmu-500"
38 - qcom,glymur-smmu-500
[all …]
H A Dnvidia,tegra30-smmu.txt1 NVIDIA Tegra 30 IOMMU H/W, SMMU (System Memory Management Unit)
4 - compatible : "nvidia,tegra30-smmu"
6 of the SMMU register blocks.
10 - nvidia,ahb : phandle to the ahb bus connected to SMMU.
13 smmu {
14 compatible = "nvidia,tegra30-smmu";
/linux/drivers/iommu/arm/arm-smmu/
H A Darm-smmu.c3 * IOMMU API for ARM architected SMMU implementations.
13 * - Non-secure access to the SMMU
18 #define pr_fmt(fmt) "arm-smmu: " fmt
41 #include "arm-smmu.h"
45 * Apparently, some Qualcomm arm64 platforms which appear to expose their SMMU
59 …"Force SMMU mappings to be installed at a particular stage of translation. A value of '1' or '2' f…
64 …domain will report an abort back to the device and will not be allowed to pass through the SMMU.");
72 static inline int arm_smmu_rpm_get(struct arm_smmu_device *smmu) in arm_smmu_rpm_get() argument
74 if (pm_runtime_enabled(smmu->dev)) in arm_smmu_rpm_get()
75 return pm_runtime_resume_and_get(smmu->dev); in arm_smmu_rpm_get()
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H A Darm-smmu-nvidia.c12 #include "arm-smmu.h"
21 * In addition, the SMMU driver needs to coordinate with the memory controller
30 * SMMU instance.
35 struct arm_smmu_device smmu; member
41 static inline struct nvidia_smmu *to_nvidia_smmu(struct arm_smmu_device *smmu) in to_nvidia_smmu() argument
43 return container_of(smmu, struct nvidia_smmu, smmu); in to_nvidia_smmu()
46 static inline void __iomem *nvidia_smmu_page(struct arm_smmu_device *smmu, in nvidia_smmu_page() argument
51 nvidia_smmu = container_of(smmu, struct nvidia_smmu, smmu); in nvidia_smmu_page()
52 return nvidia_smmu->bases[inst] + (page << smmu->pgshift); in nvidia_smmu_page()
55 static u32 nvidia_smmu_read_reg(struct arm_smmu_device *smmu, in nvidia_smmu_read_reg() argument
[all …]
H A Darm-smmu-qcom-debug.c19 #include "arm-smmu.h"
20 #include "arm-smmu-qcom.h"
59 static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu) in to_qcom_smmu() argument
61 return container_of(smmu, struct qcom_smmu, smmu); in to_qcom_smmu()
64 void qcom_smmu_tlb_sync_debug(struct arm_smmu_device *smmu) in qcom_smmu_tlb_sync_debug() argument
68 struct qcom_smmu *qsmmu = container_of(smmu, struct qcom_smmu, smmu); in qcom_smmu_tlb_sync_debug()
74 dev_err(smmu->dev, "TLB sync timed out -- SMMU may be deadlocked\n"); in qcom_smmu_tlb_sync_debug()
80 ret = qcom_scm_io_readl(smmu->ioaddr + cfg->reg_offset[QCOM_SMMU_TBU_PWR_STATUS], in qcom_smmu_tlb_sync_debug()
83 dev_err(smmu->dev, in qcom_smmu_tlb_sync_debug()
86 ret = qcom_scm_io_readl(smmu->ioaddr + cfg->reg_offset[QCOM_SMMU_STATS_SYNC_INV_TBU_ACK], in qcom_smmu_tlb_sync_debug()
[all …]
H A DMakefile4 arm_smmu-objs += arm-smmu.o arm-smmu-impl.o arm-smmu-nvidia.o
5 arm_smmu-$(CONFIG_ARM_SMMU_QCOM) += arm-smmu-qcom.o
6 arm_smmu-$(CONFIG_ARM_SMMU_QCOM_DEBUG) += arm-smmu-qcom-debug.o
/linux/drivers/iommu/
H A Dtegra-smmu.c26 struct tegra_smmu *smmu; member
59 struct tegra_smmu *smmu; member
75 static inline void smmu_writel(struct tegra_smmu *smmu, u32 value, in smmu_writel() argument
78 writel(value, smmu->regs + offset); in smmu_writel()
81 static inline u32 smmu_readl(struct tegra_smmu *smmu, unsigned long offset) in smmu_readl() argument
83 return readl(smmu->regs + offset); in smmu_readl()
92 #define SMMU_TLB_CONFIG_ACTIVE_LINES(smmu) \ argument
93 ((smmu)->soc->num_tlb_lines & (smmu)->tlb_mask)
179 static bool smmu_dma_addr_valid(struct tegra_smmu *smmu, dma_addr_t addr) in smmu_dma_addr_valid() argument
182 return (addr & smmu->pfn_mask) == addr; in smmu_dma_addr_valid()
[all …]
/linux/drivers/iommu/arm/arm-smmu-v3/
H A Darm-smmu-v3.c33 #include "arm-smmu-v3.h"
111 static void parse_driver_options(struct arm_smmu_device *smmu) in parse_driver_options() argument
116 if (of_property_read_bool(smmu->dev->of_node, in parse_driver_options()
118 smmu->options |= arm_smmu_options[i].opt; in parse_driver_options()
119 dev_notice(smmu->dev, "option %s\n", in parse_driver_options()
214 static void queue_poll_init(struct arm_smmu_device *smmu, in queue_poll_init() argument
219 qp->wfe = !!(smmu->features & ARM_SMMU_FEAT_SEV); in queue_poll_init()
371 static struct arm_smmu_cmdq *arm_smmu_get_cmdq(struct arm_smmu_device *smmu, in arm_smmu_get_cmdq() argument
376 if (smmu->impl_ops && smmu->impl_ops->get_secondary_cmdq) in arm_smmu_get_cmdq()
377 cmdq = smmu->impl_ops->get_secondary_cmdq(smmu, ent); in arm_smmu_get_cmdq()
[all …]
H A Darm-smmu-v3-iommufd.c8 #include "arm-smmu-v3.h"
14 const struct arm_smmu_impl_ops *impl_ops = master->smmu->impl_ops; in arm_smmu_hw_info()
23 return impl_ops->hw_info(master->smmu, length, type); in arm_smmu_hw_info()
30 base_idr = master->smmu->base + ARM_SMMU_IDR0; in arm_smmu_hw_info()
33 info->iidr = readl_relaxed(master->smmu->base + ARM_SMMU_IIDR); in arm_smmu_hw_info()
34 info->aidr = readl_relaxed(master->smmu->base + ARM_SMMU_AIDR); in arm_smmu_hw_info()
138 mutex_lock(&master->smmu->streams_mutex); in arm_smmu_attach_commit_vmaster()
141 mutex_unlock(&master->smmu->streams_mutex); in arm_smmu_attach_commit_vmaster()
166 if (nested_domain->vsmmu->smmu != master->smmu) in arm_smmu_attach_dev_nested()
357 struct arm_smmu_device *smmu = vsmmu->smmu; in arm_vsmmu_cache_invalidate() local
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H A Darm-smmu-v3-sva.c13 #include "arm-smmu-v3.h"
103 if (!(master->smmu->features & ARM_SMMU_FEAT_STALL_FORCE)) in arm_smmu_make_sva_cd()
115 * Note that we don't bother with S1PIE on the SMMU, we just rely on in arm_smmu_make_sva_cd()
117 * SMMU has no notion of S1POE nor GCS, so make sure that is clear if in arm_smmu_make_sva_cd()
121 dev_warn_once(master->smmu->dev, "SVA devices ignore permission overlays and GCS\n"); in arm_smmu_make_sva_cd()
128 * command queue with an address-space TLBI command, when SMMU w/o a range
149 if (!(smmu_domain->smmu->features & ARM_SMMU_FEAT_RANGE_INV)) { in arm_smmu_mm_arch_invalidate_secondary_tlbs()
158 arm_smmu_tlb_inv_asid(smmu_domain->smmu, smmu_domain->cd.asid); in arm_smmu_mm_arch_invalidate_secondary_tlbs()
194 arm_smmu_tlb_inv_asid(smmu_domain->smmu, smmu_domain->cd.asid); in arm_smmu_mm_release()
209 bool arm_smmu_sva_supported(struct arm_smmu_device *smmu) in arm_smmu_sva_supported() argument
[all …]
H A Dtegra241-cmdqv.c15 #include "arm-smmu-v3.h"
113 "This allows to disable CMDQV HW and use default SMMU internal CMDQ.");
200 * @smmu: SMMUv3 device
213 struct arm_smmu_device smmu; member
324 __arm_smmu_cmdq_skip_err(&vintf->cmdqv->smmu, &vcmdq->cmdq); in tegra241_vintf0_handle_error()
383 tegra241_cmdqv_get_cmdq(struct arm_smmu_device *smmu, in tegra241_cmdqv_get_cmdq() argument
387 container_of(smmu, struct tegra241_cmdqv, smmu); in tegra241_cmdqv_get_cmdq()
395 /* Use SMMU CMDQ if VINTF0 is uninitialized */ in tegra241_cmdqv_get_cmdq()
411 /* Unsupported CMD goes for smmu->cmdq pathway */ in tegra241_cmdqv_get_cmdq()
425 * it gets disabled. This can be done by just issuing a CMD_SYNC to SMMU CMDQ.
[all …]
H A DMakefile3 arm_smmu_v3-y := arm-smmu-v3.o
4 arm_smmu_v3-$(CONFIG_ARM_SMMU_V3_IOMMUFD) += arm-smmu-v3-iommufd.o
5 arm_smmu_v3-$(CONFIG_ARM_SMMU_V3_SVA) += arm-smmu-v3-sva.o
8 obj-$(CONFIG_ARM_SMMU_V3_KUNIT_TEST) += arm-smmu-v3-test.o
/linux/drivers/memory/tegra/
H A Dtegra210.c20 .smmu = {
36 .smmu = {
52 .smmu = {
68 .smmu = {
84 .smmu = {
100 .smmu = {
116 .smmu = {
132 .smmu = {
148 .smmu = {
164 .smmu = {
[all …]
H A Dtegra114.c31 .smmu = {
47 .smmu = {
63 .smmu = {
79 .smmu = {
95 .smmu = {
111 .smmu = {
127 .smmu = {
143 .smmu = {
159 .smmu = {
175 .smmu = {
[all …]
H A Dtegra124.c32 .smmu = {
48 .smmu = {
64 .smmu = {
80 .smmu = {
96 .smmu = {
112 .smmu = {
128 .smmu = {
144 .smmu = {
160 .smmu = {
176 .smmu = {
[all …]
H A Dtegra30.c54 .smmu = {
71 .smmu = {
88 .smmu = {
105 .smmu = {
122 .smmu = {
139 .smmu = {
156 .smmu = {
173 .smmu = {
190 .smmu = {
207 .smmu = {
[all …]
/linux/drivers/acpi/arm64/
H A Diort.c437 struct acpi_iort_smmu_v3 *smmu; in iort_get_id_mapping_index() local
449 smmu = (struct acpi_iort_smmu_v3 *)node->node_data; in iort_get_id_mapping_index()
455 if (smmu->event_gsiv && smmu->pri_gsiv && in iort_get_id_mapping_index()
456 smmu->gerr_gsiv && smmu->sync_gsiv) in iort_get_id_mapping_index()
458 } else if (!(smmu->flags & ACPI_IORT_SMMU_V3_DEVICEID_VALID)) { in iort_get_id_mapping_index()
462 if (smmu->id_mapping_index >= node->mapping_count) { in iort_get_id_mapping_index()
468 return smmu->id_mapping_index; in iort_get_id_mapping_index()
561 * as NC (named component) -> SMMU -> ITS. If the type is matched, in iort_node_map_platform_id()
581 * device (such as SMMU, PMCG),its iort node already cached in iort_find_dev_node()
1009 struct acpi_iort_node *smmu, in iort_get_rmrs() argument
[all …]
/linux/arch/arm64/boot/dts/marvell/
H A Darmada-8040.dtsi14 <0x0 &smmu 0x480 0x20>,
15 <0x100 &smmu 0x4a0 0x20>,
16 <0x200 &smmu 0x4c0 0x20>;
30 iommus = <&smmu 0x444>;
34 iommus = <&smmu 0x445>;
38 iommus = <&smmu 0x440>;
42 iommus = <&smmu 0x441>;
46 iommus = <&smmu 0x454>;
50 iommus = <&smmu 0x450>;
54 iommus = <&smmu 0x451>;
H A Darmada-7040.dtsi14 <0x0 &smmu 0x480 0x20>,
15 <0x100 &smmu 0x4a0 0x20>,
16 <0x200 &smmu 0x4c0 0x20>;
21 iommus = <&smmu 0x444>;
25 iommus = <&smmu 0x445>;
29 iommus = <&smmu 0x440>;
33 iommus = <&smmu 0x441>;
H A Dcn9130-crb-A.dts22 <0x0 &smmu 0x480 0x20>,
23 <0x100 &smmu 0x4a0 0x20>,
24 <0x200 &smmu 0x4c0 0x20>;
/linux/Documentation/devicetree/bindings/display/
H A Darm,komeda.yaml102 iommus = <&smmu 0>, <&smmu 1>, <&smmu 2>, <&smmu 3>,
103 <&smmu 8>,
104 <&smmu 4>, <&smmu 5>, <&smmu 6>, <&smmu 7>,
105 <&smmu 9>;
/linux/include/linux/
H A Dadreno-smmu-priv.h38 * struct adreno_smmu_priv - private interface between adreno-smmu and GPU
40 * @cookie: An opque token provided by adreno-smmu and passed
59 * The GPU driver (drm/msm) and adreno-smmu work together for controlling
60 * the GPU's SMMU instance. This is by necessity, as the GPU is directly
61 * updating the SMMU for context switches, while on the other hand we do
62 * not want to duplicate all of the initial setup logic from arm-smmu.
/linux/include/soc/tegra/
H A Dmc.h35 * Tegra SMMU, whereas on Tegra186 and later this is the ID used to override the ARM SMMU
46 /* Tegra SMMU enable (Tegra210 and earlier) */
50 } smmu; member
104 void tegra_smmu_remove(struct tegra_smmu *smmu);
113 static inline void tegra_smmu_remove(struct tegra_smmu *smmu) in tegra_smmu_remove() argument
186 const struct tegra_smmu_soc *smmu; member
204 struct tegra_smmu *smmu; member
/linux/Documentation/devicetree/bindings/perf/
H A Darm,smmu-v3-pmcg.yaml4 $id: http://devicetree.org/schemas/perf/arm,smmu-v3-pmcg.yaml#
25 - const: arm,smmu-v3-pmcg
26 - const: arm,smmu-v3-pmcg
57 compatible = "arm,smmu-v3-pmcg";
65 compatible = "arm,smmu-v3-pmcg";
/linux/arch/arm64/boot/dts/xilinx/
H A Dversal-net-vn-x-b2197-01-revA.dts79 iommus = <&smmu 0x235>;
93 iommus = <&smmu 0x245>;
100 iommus = <&smmu 0x243>;
114 &smmu {

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