1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2022, Konrad Dybcio <konrad.dybcio@somainline.org> 4 */ 5 6#include <dt-bindings/clock/qcom,rpmcc.h> 7#include <dt-bindings/clock/qcom,sm6375-gcc.h> 8#include <dt-bindings/clock/qcom,sm6375-gpucc.h> 9#include <dt-bindings/dma/qcom-gpi.h> 10#include <dt-bindings/firmware/qcom,scm.h> 11#include <dt-bindings/interconnect/qcom,osm-l3.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/mailbox/qcom-ipcc.h> 14#include <dt-bindings/power/qcom-rpmpd.h> 15 16/ { 17 interrupt-parent = <&intc>; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 chosen { }; 23 24 clocks { 25 xo_board_clk: xo-board-clk { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 }; 29 30 sleep_clk: sleep-clk { 31 compatible = "fixed-clock"; 32 clock-frequency = <32764>; 33 #clock-cells = <0>; 34 }; 35 }; 36 37 cpus { 38 #address-cells = <2>; 39 #size-cells = <0>; 40 41 cpu0: cpu@0 { 42 device_type = "cpu"; 43 compatible = "qcom,kryo660"; 44 reg = <0x0 0x0>; 45 clocks = <&cpufreq_hw 0>; 46 enable-method = "psci"; 47 next-level-cache = <&l2_0>; 48 qcom,freq-domain = <&cpufreq_hw 0>; 49 operating-points-v2 = <&cpu0_opp_table>; 50 interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>; 51 power-domains = <&cpu_pd0>; 52 power-domain-names = "psci"; 53 #cooling-cells = <2>; 54 l2_0: l2-cache { 55 compatible = "cache"; 56 cache-level = <2>; 57 cache-unified; 58 next-level-cache = <&l3_0>; 59 l3_0: l3-cache { 60 compatible = "cache"; 61 cache-level = <3>; 62 cache-unified; 63 }; 64 }; 65 }; 66 67 cpu1: cpu@100 { 68 device_type = "cpu"; 69 compatible = "qcom,kryo660"; 70 reg = <0x0 0x100>; 71 clocks = <&cpufreq_hw 0>; 72 enable-method = "psci"; 73 next-level-cache = <&l2_100>; 74 qcom,freq-domain = <&cpufreq_hw 0>; 75 operating-points-v2 = <&cpu0_opp_table>; 76 interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>; 77 power-domains = <&cpu_pd1>; 78 power-domain-names = "psci"; 79 #cooling-cells = <2>; 80 l2_100: l2-cache { 81 compatible = "cache"; 82 cache-level = <2>; 83 cache-unified; 84 next-level-cache = <&l3_0>; 85 }; 86 }; 87 88 cpu2: cpu@200 { 89 device_type = "cpu"; 90 compatible = "qcom,kryo660"; 91 reg = <0x0 0x200>; 92 clocks = <&cpufreq_hw 0>; 93 enable-method = "psci"; 94 next-level-cache = <&l2_200>; 95 qcom,freq-domain = <&cpufreq_hw 0>; 96 operating-points-v2 = <&cpu0_opp_table>; 97 interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>; 98 power-domains = <&cpu_pd2>; 99 power-domain-names = "psci"; 100 #cooling-cells = <2>; 101 l2_200: l2-cache { 102 compatible = "cache"; 103 cache-level = <2>; 104 cache-unified; 105 next-level-cache = <&l3_0>; 106 }; 107 }; 108 109 cpu3: cpu@300 { 110 device_type = "cpu"; 111 compatible = "qcom,kryo660"; 112 reg = <0x0 0x300>; 113 clocks = <&cpufreq_hw 0>; 114 enable-method = "psci"; 115 next-level-cache = <&l2_300>; 116 qcom,freq-domain = <&cpufreq_hw 0>; 117 operating-points-v2 = <&cpu0_opp_table>; 118 interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>; 119 power-domains = <&cpu_pd3>; 120 power-domain-names = "psci"; 121 #cooling-cells = <2>; 122 l2_300: l2-cache { 123 compatible = "cache"; 124 cache-level = <2>; 125 cache-unified; 126 next-level-cache = <&l3_0>; 127 }; 128 }; 129 130 cpu4: cpu@400 { 131 device_type = "cpu"; 132 compatible = "qcom,kryo660"; 133 reg = <0x0 0x400>; 134 clocks = <&cpufreq_hw 0>; 135 enable-method = "psci"; 136 next-level-cache = <&l2_400>; 137 qcom,freq-domain = <&cpufreq_hw 0>; 138 operating-points-v2 = <&cpu0_opp_table>; 139 interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>; 140 power-domains = <&cpu_pd4>; 141 power-domain-names = "psci"; 142 #cooling-cells = <2>; 143 l2_400: l2-cache { 144 compatible = "cache"; 145 cache-level = <2>; 146 cache-unified; 147 next-level-cache = <&l3_0>; 148 }; 149 }; 150 151 cpu5: cpu@500 { 152 device_type = "cpu"; 153 compatible = "qcom,kryo660"; 154 reg = <0x0 0x500>; 155 clocks = <&cpufreq_hw 0>; 156 enable-method = "psci"; 157 next-level-cache = <&l2_500>; 158 qcom,freq-domain = <&cpufreq_hw 0>; 159 operating-points-v2 = <&cpu0_opp_table>; 160 interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>; 161 power-domains = <&cpu_pd5>; 162 power-domain-names = "psci"; 163 #cooling-cells = <2>; 164 l2_500: l2-cache { 165 compatible = "cache"; 166 cache-level = <2>; 167 cache-unified; 168 next-level-cache = <&l3_0>; 169 }; 170 }; 171 172 cpu6: cpu@600 { 173 device_type = "cpu"; 174 compatible = "qcom,kryo660"; 175 reg = <0x0 0x600>; 176 clocks = <&cpufreq_hw 1>; 177 enable-method = "psci"; 178 next-level-cache = <&l2_600>; 179 qcom,freq-domain = <&cpufreq_hw 1>; 180 operating-points-v2 = <&cpu6_opp_table>; 181 interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>; 182 power-domains = <&cpu_pd6>; 183 power-domain-names = "psci"; 184 #cooling-cells = <2>; 185 l2_600: l2-cache { 186 compatible = "cache"; 187 cache-level = <2>; 188 cache-unified; 189 next-level-cache = <&l3_0>; 190 }; 191 }; 192 193 cpu7: cpu@700 { 194 device_type = "cpu"; 195 compatible = "qcom,kryo660"; 196 reg = <0x0 0x700>; 197 clocks = <&cpufreq_hw 1>; 198 enable-method = "psci"; 199 next-level-cache = <&l2_700>; 200 qcom,freq-domain = <&cpufreq_hw 1>; 201 operating-points-v2 = <&cpu6_opp_table>; 202 interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>; 203 power-domains = <&cpu_pd7>; 204 power-domain-names = "psci"; 205 #cooling-cells = <2>; 206 l2_700: l2-cache { 207 compatible = "cache"; 208 cache-level = <2>; 209 cache-unified; 210 next-level-cache = <&l3_0>; 211 }; 212 }; 213 214 cpu-map { 215 cluster0 { 216 core0 { 217 cpu = <&cpu0>; 218 }; 219 220 core1 { 221 cpu = <&cpu1>; 222 }; 223 224 core2 { 225 cpu = <&cpu2>; 226 }; 227 228 core3 { 229 cpu = <&cpu3>; 230 }; 231 232 core4 { 233 cpu = <&cpu4>; 234 }; 235 236 core5 { 237 cpu = <&cpu5>; 238 }; 239 240 core6 { 241 cpu = <&cpu6>; 242 }; 243 244 core7 { 245 cpu = <&cpu7>; 246 }; 247 }; 248 }; 249 250 idle-states { 251 entry-method = "psci"; 252 253 little_cpu_sleep_0: cpu-sleep-0-0 { 254 compatible = "arm,idle-state"; 255 idle-state-name = "silver-power-collapse"; 256 arm,psci-suspend-param = <0x40000003>; 257 entry-latency-us = <549>; 258 exit-latency-us = <901>; 259 min-residency-us = <1774>; 260 local-timer-stop; 261 }; 262 263 little_cpu_sleep_1: cpu-sleep-0-1 { 264 compatible = "arm,idle-state"; 265 idle-state-name = "silver-rail-power-collapse"; 266 arm,psci-suspend-param = <0x40000004>; 267 entry-latency-us = <702>; 268 exit-latency-us = <915>; 269 min-residency-us = <4001>; 270 local-timer-stop; 271 }; 272 273 big_cpu_sleep_0: cpu-sleep-1-0 { 274 compatible = "arm,idle-state"; 275 idle-state-name = "gold-power-collapse"; 276 arm,psci-suspend-param = <0x40000003>; 277 entry-latency-us = <523>; 278 exit-latency-us = <1244>; 279 min-residency-us = <2207>; 280 local-timer-stop; 281 }; 282 283 big_cpu_sleep_1: cpu-sleep-1-1 { 284 compatible = "arm,idle-state"; 285 idle-state-name = "gold-rail-power-collapse"; 286 arm,psci-suspend-param = <0x40000004>; 287 entry-latency-us = <526>; 288 exit-latency-us = <1854>; 289 min-residency-us = <5555>; 290 local-timer-stop; 291 }; 292 }; 293 294 domain-idle-states { 295 cluster_sleep_0: cluster-sleep-0 { 296 compatible = "domain-idle-state"; 297 arm,psci-suspend-param = <0x41000044>; 298 entry-latency-us = <2752>; 299 exit-latency-us = <3048>; 300 min-residency-us = <6118>; 301 }; 302 }; 303 }; 304 305 firmware { 306 scm { 307 compatible = "qcom,scm-sm6375", "qcom,scm"; 308 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 309 clock-names = "core"; 310 #reset-cells = <1>; 311 }; 312 }; 313 314 mpm: interrupt-controller { 315 compatible = "qcom,mpm"; 316 qcom,rpm-msg-ram = <&apss_mpm>; 317 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 318 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_SMP2P>; 319 interrupt-controller; 320 #interrupt-cells = <2>; 321 #power-domain-cells = <0>; 322 interrupt-parent = <&intc>; 323 qcom,mpm-pin-count = <96>; 324 qcom,mpm-pin-map = <5 296>, /* Soundwire wake_irq */ 325 <12 422>, /* DWC3 ss_phy_irq */ 326 <86 183>, /* MPM wake, SPMI */ 327 <89 314>, /* TSENS0 0C */ 328 <90 315>, /* TSENS1 0C */ 329 <93 164>, /* DWC3 dm_hs_phy_irq */ 330 <94 165>; /* DWC3 dp_hs_phy_irq */ 331 }; 332 333 memory@80000000 { 334 device_type = "memory"; 335 /* We expect the bootloader to fill in the size */ 336 reg = <0x0 0x80000000 0x0 0x0>; 337 }; 338 339 cpu0_opp_table: opp-table-cpu0 { 340 compatible = "operating-points-v2"; 341 opp-shared; 342 343 opp-300000000 { 344 opp-hz = /bits/ 64 <300000000>; 345 opp-peak-kBps = <(300000 * 32)>; 346 }; 347 348 opp-576000000 { 349 opp-hz = /bits/ 64 <576000000>; 350 opp-peak-kBps = <(556800 * 32)>; 351 }; 352 353 opp-691200000 { 354 opp-hz = /bits/ 64 <691200000>; 355 opp-peak-kBps = <(652800 * 32)>; 356 }; 357 358 opp-940800000 { 359 opp-hz = /bits/ 64 <940800000>; 360 opp-peak-kBps = <(921600 * 32)>; 361 }; 362 363 opp-1113600000 { 364 opp-hz = /bits/ 64 <1113600000>; 365 opp-peak-kBps = <(921600 * 32)>; 366 }; 367 368 opp-1324800000 { 369 opp-hz = /bits/ 64 <1324800000>; 370 opp-peak-kBps = <(1171200 * 32)>; 371 }; 372 373 opp-1516800000 { 374 opp-hz = /bits/ 64 <1516800000>; 375 opp-peak-kBps = <(1497600 * 32)>; 376 }; 377 378 opp-1651200000 { 379 opp-hz = /bits/ 64 <1651200000>; 380 opp-peak-kBps = <(1497600 * 32)>; 381 }; 382 383 opp-1708800000 { 384 opp-hz = /bits/ 64 <1708800000>; 385 opp-peak-kBps = <(1497600 * 32)>; 386 }; 387 388 opp-1804800000 { 389 opp-hz = /bits/ 64 <1804800000>; 390 opp-peak-kBps = <(1497600 * 32)>; 391 }; 392 }; 393 394 cpu6_opp_table: opp-table-cpu6 { 395 compatible = "operating-points-v2"; 396 opp-shared; 397 398 opp-691200000 { 399 opp-hz = /bits/ 64 <691200000>; 400 opp-peak-kBps = <(556800 * 32)>; 401 }; 402 403 opp-940800000 { 404 opp-hz = /bits/ 64 <940800000>; 405 opp-peak-kBps = <(921600 * 32)>; 406 }; 407 408 opp-1228800000 { 409 opp-hz = /bits/ 64 <1228800000>; 410 opp-peak-kBps = <(1171200 * 32)>; 411 }; 412 413 opp-1401600000 { 414 opp-hz = /bits/ 64 <1401600000>; 415 opp-peak-kBps = <(1382400 * 32)>; 416 }; 417 418 opp-1516800000 { 419 opp-hz = /bits/ 64 <1516800000>; 420 opp-peak-kBps = <(1497600 * 32)>; 421 }; 422 423 opp-1651200000 { 424 opp-hz = /bits/ 64 <1651200000>; 425 opp-peak-kBps = <(1497600 * 32)>; 426 }; 427 428 opp-1804800000 { 429 opp-hz = /bits/ 64 <1804800000>; 430 opp-peak-kBps = <(1497600 * 32)>; 431 }; 432 433 opp-1900800000 { 434 opp-hz = /bits/ 64 <1900800000>; 435 opp-peak-kBps = <(1497600 * 32)>; 436 }; 437 438 opp-2054400000 { 439 opp-hz = /bits/ 64 <2054400000>; 440 opp-peak-kBps = <(1497600 * 32)>; 441 }; 442 443 opp-2208000000 { 444 opp-hz = /bits/ 64 <2208000000>; 445 opp-peak-kBps = <(1497600 * 32)>; 446 }; 447 }; 448 449 pmu { 450 compatible = "arm,armv8-pmuv3"; 451 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 452 }; 453 454 psci { 455 compatible = "arm,psci-1.0"; 456 method = "smc"; 457 458 cpu_pd0: power-domain-cpu0 { 459 #power-domain-cells = <0>; 460 power-domains = <&cluster_pd>; 461 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 462 }; 463 464 cpu_pd1: power-domain-cpu1 { 465 #power-domain-cells = <0>; 466 power-domains = <&cluster_pd>; 467 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 468 }; 469 470 cpu_pd2: power-domain-cpu2 { 471 #power-domain-cells = <0>; 472 power-domains = <&cluster_pd>; 473 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 474 }; 475 476 cpu_pd3: power-domain-cpu3 { 477 #power-domain-cells = <0>; 478 power-domains = <&cluster_pd>; 479 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 480 }; 481 482 cpu_pd4: power-domain-cpu4 { 483 #power-domain-cells = <0>; 484 power-domains = <&cluster_pd>; 485 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 486 }; 487 488 cpu_pd5: power-domain-cpu5 { 489 #power-domain-cells = <0>; 490 power-domains = <&cluster_pd>; 491 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 492 }; 493 494 cpu_pd6: power-domain-cpu6 { 495 #power-domain-cells = <0>; 496 power-domains = <&cluster_pd>; 497 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 498 }; 499 500 cpu_pd7: power-domain-cpu7 { 501 #power-domain-cells = <0>; 502 power-domains = <&cluster_pd>; 503 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 504 }; 505 506 cluster_pd: power-domain-cpu-cluster0 { 507 #power-domain-cells = <0>; 508 power-domains = <&mpm>; 509 domain-idle-states = <&cluster_sleep_0>; 510 }; 511 }; 512 513 qup_opp_table: opp-table-qup { 514 compatible = "operating-points-v2"; 515 516 opp-75000000 { 517 opp-hz = /bits/ 64 <75000000>; 518 required-opps = <&rpmpd_opp_low_svs>; 519 }; 520 521 opp-100000000 { 522 opp-hz = /bits/ 64 <100000000>; 523 required-opps = <&rpmpd_opp_svs>; 524 }; 525 526 opp-128000000 { 527 opp-hz = /bits/ 64 <128000000>; 528 required-opps = <&rpmpd_opp_nom>; 529 }; 530 }; 531 532 reserved_memory: reserved-memory { 533 #address-cells = <2>; 534 #size-cells = <2>; 535 ranges; 536 537 hyp_mem: hypervisor@80000000 { 538 reg = <0 0x80000000 0 0x600000>; 539 no-map; 540 }; 541 542 xbl_aop_mem: xbl-aop@80700000 { 543 reg = <0 0x80700000 0 0x100000>; 544 no-map; 545 }; 546 547 reserved_xbl_uefi: xbl-uefi-res@80880000 { 548 reg = <0 0x80880000 0 0x14000>; 549 no-map; 550 }; 551 552 smem_mem: smem@80900000 { 553 compatible = "qcom,smem"; 554 reg = <0 0x80900000 0 0x200000>; 555 hwlocks = <&tcsr_mutex 3>; 556 no-map; 557 }; 558 559 fw_mem: fw@80b00000 { 560 reg = <0 0x80b00000 0 0x100000>; 561 no-map; 562 }; 563 564 cdsp_secure_heap_mem: cdsp-sec-heap@80c00000 { 565 reg = <0 0x80c00000 0 0x1e00000>; 566 no-map; 567 }; 568 569 dfps_data_mem: dpfs-data@85e00000 { 570 reg = <0 0x85e00000 0 0x100000>; 571 no-map; 572 }; 573 574 pil_wlan_mem: pil-wlan@86500000 { 575 reg = <0 0x86500000 0 0x200000>; 576 no-map; 577 }; 578 579 pil_adsp_mem: pil-adsp@86700000 { 580 reg = <0 0x86700000 0 0x2000000>; 581 no-map; 582 }; 583 584 pil_cdsp_mem: pil-cdsp@88700000 { 585 reg = <0 0x88700000 0 0x1e00000>; 586 no-map; 587 }; 588 589 pil_video_mem: pil-video@8a500000 { 590 reg = <0 0x8a500000 0 0x500000>; 591 no-map; 592 }; 593 594 pil_ipa_fw_mem: pil-ipa-fw@8aa00000 { 595 reg = <0 0x8aa00000 0 0x10000>; 596 no-map; 597 }; 598 599 pil_ipa_gsi_mem: pil-ipa-gsi@8aa10000 { 600 reg = <0 0x8aa10000 0 0xa000>; 601 no-map; 602 }; 603 604 pil_gpu_micro_code_mem: pil-gpu-ucode@8aa1a000 { 605 reg = <0 0x8aa1a000 0 0x2000>; 606 no-map; 607 }; 608 609 pil_mpss_wlan_mem: pil-mpss-wlan@8b800000 { 610 reg = <0 0x8b800000 0 0x10000000>; 611 no-map; 612 }; 613 614 removed_mem: removed@c0000000 { 615 reg = <0 0xc0000000 0 0x5100000>; 616 no-map; 617 }; 618 619 rmtfs_mem: rmtfs@f3900000 { 620 compatible = "qcom,rmtfs-mem"; 621 reg = <0 0xf3900000 0 0x280000>; 622 no-map; 623 624 qcom,client-id = <1>; 625 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>; 626 }; 627 628 debug_mem: debug@ffb00000 { 629 reg = <0 0xffb00000 0 0xc0000>; 630 no-map; 631 }; 632 633 last_log_mem: lastlog@ffbc0000 { 634 reg = <0 0xffbc0000 0 0x80000>; 635 no-map; 636 }; 637 638 cmdline_region: cmdline@ffd00000 { 639 reg = <0 0xffd00000 0 0x1000>; 640 no-map; 641 }; 642 }; 643 644 rpm: remoteproc { 645 compatible = "qcom,sm6375-rpm-proc", "qcom,rpm-proc"; 646 647 glink-edge { 648 compatible = "qcom,glink-rpm"; 649 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 650 IPCC_MPROC_SIGNAL_GLINK_QMP 651 IRQ_TYPE_EDGE_RISING>; 652 qcom,rpm-msg-ram = <&rpm_msg_ram>; 653 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 654 655 rpm_requests: rpm-requests { 656 compatible = "qcom,rpm-sm6375", "qcom,glink-smd-rpm"; 657 qcom,glink-channels = "rpm_requests"; 658 659 rpmcc: clock-controller { 660 compatible = "qcom,rpmcc-sm6375", "qcom,rpmcc"; 661 clocks = <&xo_board_clk>; 662 clock-names = "xo"; 663 #clock-cells = <1>; 664 }; 665 666 rpmpd: power-controller { 667 compatible = "qcom,sm6375-rpmpd"; 668 #power-domain-cells = <1>; 669 operating-points-v2 = <&rpmpd_opp_table>; 670 671 rpmpd_opp_table: opp-table { 672 compatible = "operating-points-v2"; 673 674 rpmpd_opp_ret: opp1 { 675 opp-level = <RPM_SMD_LEVEL_RETENTION>; 676 }; 677 678 rpmpd_opp_min_svs: opp2 { 679 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 680 }; 681 682 rpmpd_opp_low_svs: opp3 { 683 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 684 }; 685 686 rpmpd_opp_svs: opp4 { 687 opp-level = <RPM_SMD_LEVEL_SVS>; 688 }; 689 690 rpmpd_opp_svs_plus: opp5 { 691 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 692 }; 693 694 rpmpd_opp_nom: opp6 { 695 opp-level = <RPM_SMD_LEVEL_NOM>; 696 }; 697 698 rpmpd_opp_nom_plus: opp7 { 699 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 700 }; 701 702 rpmpd_opp_turbo: opp8 { 703 opp-level = <RPM_SMD_LEVEL_TURBO>; 704 }; 705 706 rpmpd_opp_turbo_no_cpr: opp9 { 707 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 708 }; 709 }; 710 }; 711 }; 712 }; 713 }; 714 715 smp2p-adsp { 716 compatible = "qcom,smp2p"; 717 qcom,smem = <443>, <429>; 718 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 719 IPCC_MPROC_SIGNAL_SMP2P 720 IRQ_TYPE_EDGE_RISING>; 721 mboxes = <&ipcc IPCC_CLIENT_LPASS 722 IPCC_MPROC_SIGNAL_SMP2P>; 723 724 qcom,local-pid = <0>; 725 qcom,remote-pid = <2>; 726 727 smp2p_adsp_out: master-kernel { 728 qcom,entry-name = "master-kernel"; 729 #qcom,smem-state-cells = <1>; 730 }; 731 732 smp2p_adsp_in: slave-kernel { 733 qcom,entry-name = "slave-kernel"; 734 interrupt-controller; 735 #interrupt-cells = <2>; 736 }; 737 }; 738 739 smp2p-cdsp { 740 compatible = "qcom,smp2p"; 741 qcom,smem = <94>, <432>; 742 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 743 IPCC_MPROC_SIGNAL_SMP2P 744 IRQ_TYPE_EDGE_RISING>; 745 mboxes = <&ipcc IPCC_CLIENT_CDSP 746 IPCC_MPROC_SIGNAL_SMP2P>; 747 748 qcom,local-pid = <0>; 749 qcom,remote-pid = <5>; 750 751 smp2p_cdsp_out: master-kernel { 752 qcom,entry-name = "master-kernel"; 753 #qcom,smem-state-cells = <1>; 754 }; 755 756 smp2p_cdsp_in: slave-kernel { 757 qcom,entry-name = "slave-kernel"; 758 interrupt-controller; 759 #interrupt-cells = <2>; 760 }; 761 }; 762 763 smp2p-modem { 764 compatible = "qcom,smp2p"; 765 qcom,smem = <435>, <428>; 766 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 767 IPCC_MPROC_SIGNAL_SMP2P 768 IRQ_TYPE_EDGE_RISING>; 769 mboxes = <&ipcc IPCC_CLIENT_MPSS 770 IPCC_MPROC_SIGNAL_SMP2P>; 771 772 qcom,local-pid = <0>; 773 qcom,remote-pid = <1>; 774 775 smp2p_modem_out: master-kernel { 776 qcom,entry-name = "master-kernel"; 777 #qcom,smem-state-cells = <1>; 778 }; 779 780 smp2p_modem_in: slave-kernel { 781 qcom,entry-name = "slave-kernel"; 782 interrupt-controller; 783 #interrupt-cells = <2>; 784 }; 785 786 ipa_smp2p_out: ipa-ap-to-modem { 787 qcom,entry-name = "ipa"; 788 #qcom,smem-state-cells = <1>; 789 }; 790 791 ipa_smp2p_in: ipa-modem-to-ap { 792 qcom,entry-name = "ipa"; 793 interrupt-controller; 794 #interrupt-cells = <2>; 795 }; 796 797 wlan_smp2p_in: wlan-wpss-to-ap { 798 qcom,entry-name = "wlan"; 799 interrupt-controller; 800 #interrupt-cells = <2>; 801 }; 802 }; 803 804 soc: soc@0 { 805 #address-cells = <2>; 806 #size-cells = <2>; 807 ranges = <0 0 0 0 0x10 0>; 808 dma-ranges = <0 0 0 0 0x10 0>; 809 compatible = "simple-bus"; 810 811 ipcc: mailbox@208000 { 812 compatible = "qcom,sm6375-ipcc", "qcom,ipcc"; 813 reg = <0 0x00208000 0 0x1000>; 814 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>; 815 interrupt-controller; 816 #interrupt-cells = <3>; 817 #mbox-cells = <2>; 818 }; 819 820 tcsr_mutex: hwlock@340000 { 821 compatible = "qcom,tcsr-mutex"; 822 reg = <0x0 0x00340000 0x0 0x40000>; 823 #hwlock-cells = <1>; 824 }; 825 826 tlmm: pinctrl@500000 { 827 compatible = "qcom,sm6375-tlmm"; 828 reg = <0 0x00500000 0 0x800000>; 829 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 830 gpio-ranges = <&tlmm 0 0 157>; 831 wakeup-parent = <&mpm>; 832 interrupt-controller; 833 gpio-controller; 834 #interrupt-cells = <2>; 835 #gpio-cells = <2>; 836 837 sdc2_off_state: sdc2-off-state { 838 clk-pins { 839 pins = "sdc2_clk"; 840 drive-strength = <2>; 841 bias-disable; 842 }; 843 844 cmd-pins { 845 pins = "sdc2_cmd"; 846 drive-strength = <2>; 847 bias-pull-up; 848 }; 849 850 data-pins { 851 pins = "sdc2_data"; 852 drive-strength = <2>; 853 bias-pull-up; 854 }; 855 }; 856 857 sdc2_on_state: sdc2-on-state { 858 clk-pins { 859 pins = "sdc2_clk"; 860 drive-strength = <16>; 861 bias-disable; 862 }; 863 864 cmd-pins { 865 pins = "sdc2_cmd"; 866 drive-strength = <10>; 867 bias-pull-up; 868 }; 869 870 data-pins { 871 pins = "sdc2_data"; 872 drive-strength = <10>; 873 bias-pull-up; 874 }; 875 }; 876 877 qup_i2c0_default: qup-i2c0-default-state { 878 pins = "gpio0", "gpio1"; 879 function = "qup00"; 880 drive-strength = <2>; 881 bias-pull-up; 882 }; 883 884 qup_i2c1_default: qup-i2c1-default-state { 885 pins = "gpio61", "gpio62"; 886 function = "qup01"; 887 drive-strength = <2>; 888 bias-pull-up; 889 }; 890 891 qup_i2c2_default: qup-i2c2-default-state { 892 pins = "gpio45", "gpio46"; 893 function = "qup02"; 894 drive-strength = <2>; 895 bias-pull-up; 896 }; 897 898 qup_i2c8_default: qup-i2c8-default-state { 899 pins = "gpio19", "gpio20"; 900 /* TLMM, GCC and vendor DT all have different indices.. */ 901 function = "qup12"; 902 drive-strength = <2>; 903 bias-pull-up; 904 }; 905 906 qup_i2c10_default: qup-i2c10-default-state { 907 pins = "gpio4", "gpio5"; 908 function = "qup10"; 909 drive-strength = <2>; 910 bias-pull-up; 911 }; 912 913 qup_spi0_default: qup-spi0-default-state { 914 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 915 function = "qup00"; 916 drive-strength = <6>; 917 bias-disable; 918 }; 919 920 qup_uart1_default: qup-uart1-default-state { 921 cts-pins { 922 pins = "gpio61"; 923 function = "qup01"; 924 drive-strength = <2>; 925 bias-pull-down; 926 }; 927 928 rts-pins { 929 pins = "gpio62"; 930 function = "qup01"; 931 drive-strength = <2>; 932 bias-disable; 933 }; 934 935 tx-pins { 936 pins = "gpio63"; 937 function = "qup01"; 938 drive-strength = <2>; 939 bias-disable; 940 }; 941 942 rx-pins { 943 pins = "gpio64"; 944 function = "qup01"; 945 drive-strength = <2>; 946 bias-pull-up; 947 }; 948 }; 949 }; 950 951 gcc: clock-controller@1400000 { 952 compatible = "qcom,sm6375-gcc"; 953 reg = <0 0x01400000 0 0x1f0000>; 954 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 955 <&rpmcc RPM_SMD_XO_A_CLK_SRC>, 956 <&sleep_clk>; 957 #power-domain-cells = <1>; 958 #clock-cells = <1>; 959 #reset-cells = <1>; 960 }; 961 962 usb_1_hsphy: phy@162b000 { 963 compatible = "qcom,sm6375-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy"; 964 reg = <0 0x0162b000 0 0x400>; 965 966 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 967 clock-names = "ref"; 968 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 969 #phy-cells = <0>; 970 971 status = "disabled"; 972 }; 973 974 refgen: regulator@162f000 { 975 compatible = "qcom,sm6375-refgen-regulator", 976 "qcom,sm8250-refgen-regulator"; 977 reg = <0x0 0x0162f000 0x0 0x84>; 978 }; 979 980 spmi_bus: spmi@1c40000 { 981 compatible = "qcom,spmi-pmic-arb"; 982 reg = <0 0x01c40000 0 0x1100>, 983 <0 0x01e00000 0 0x2000000>, 984 <0 0x03e00000 0 0x100000>, 985 <0 0x03f00000 0 0xa0000>, 986 <0 0x01c0a000 0 0x26000>; 987 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 988 interrupt-names = "periph_irq"; 989 interrupts-extended = <&mpm 86 IRQ_TYPE_LEVEL_HIGH>; 990 qcom,ee = <0>; 991 qcom,channel = <0>; 992 #address-cells = <2>; 993 #size-cells = <0>; 994 interrupt-controller; 995 #interrupt-cells = <4>; 996 }; 997 998 tsens0: thermal-sensor@4411000 { 999 compatible = "qcom,sm6375-tsens", "qcom,tsens-v2"; 1000 reg = <0 0x04411000 0 0x140>, /* TM */ 1001 <0 0x04410000 0 0x20>; /* SROT */ 1002 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 1003 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1004 interrupt-names = "uplow", "critical"; 1005 #thermal-sensor-cells = <1>; 1006 #qcom,sensors = <15>; 1007 }; 1008 1009 tsens1: thermal-sensor@4413000 { 1010 compatible = "qcom,sm6375-tsens", "qcom,tsens-v2"; 1011 reg = <0 0x04413000 0 0x140>, /* TM */ 1012 <0 0x04412000 0 0x20>; /* SROT */ 1013 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1014 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>; 1015 interrupt-names = "uplow", "critical"; 1016 #thermal-sensor-cells = <1>; 1017 #qcom,sensors = <11>; 1018 }; 1019 1020 rpm_msg_ram: sram@45f0000 { 1021 compatible = "qcom,rpm-msg-ram", "mmio-sram"; 1022 reg = <0 0x045f0000 0 0x7000>; 1023 #address-cells = <1>; 1024 #size-cells = <1>; 1025 ranges = <0 0x0 0x045f0000 0x7000>; 1026 1027 apss_mpm: sram@1b8 { 1028 reg = <0x1b8 0x48>; 1029 }; 1030 }; 1031 1032 sram@4690000 { 1033 compatible = "qcom,rpm-stats"; 1034 reg = <0 0x04690000 0 0x400>; 1035 }; 1036 1037 sdhc_2: mmc@4784000 { 1038 compatible = "qcom,sm6375-sdhci", "qcom,sdhci-msm-v5"; 1039 reg = <0 0x04784000 0 0x1000>; 1040 1041 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 1042 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1043 interrupt-names = "hc_irq", "pwr_irq"; 1044 1045 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1046 <&gcc GCC_SDCC2_APPS_CLK>, 1047 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1048 clock-names = "iface", "core", "xo"; 1049 resets = <&gcc GCC_SDCC2_BCR>; 1050 iommus = <&apps_smmu 0x40 0x0>; 1051 1052 pinctrl-0 = <&sdc2_on_state>; 1053 pinctrl-1 = <&sdc2_off_state>; 1054 pinctrl-names = "default", "sleep"; 1055 1056 qcom,dll-config = <0x0007642c>; 1057 qcom,ddr-config = <0x80040868>; 1058 power-domains = <&rpmpd SM6375_VDDCX>; 1059 operating-points-v2 = <&sdhc2_opp_table>; 1060 bus-width = <4>; 1061 1062 status = "disabled"; 1063 1064 sdhc2_opp_table: opp-table { 1065 compatible = "operating-points-v2"; 1066 1067 opp-100000000 { 1068 opp-hz = /bits/ 64 <100000000>; 1069 required-opps = <&rpmpd_opp_low_svs>; 1070 }; 1071 1072 opp-202000000 { 1073 opp-hz = /bits/ 64 <202000000>; 1074 required-opps = <&rpmpd_opp_svs_plus>; 1075 }; 1076 }; 1077 }; 1078 1079 gpi_dma0: dma-controller@4a00000 { 1080 compatible = "qcom,sm6375-gpi-dma", "qcom,sm6350-gpi-dma"; 1081 reg = <0 0x04a00000 0 0x60000>; 1082 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1083 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1084 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1085 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1086 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1087 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1088 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1089 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1090 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1091 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 1092 dma-channels = <10>; 1093 dma-channel-mask = <0x1f>; 1094 iommus = <&apps_smmu 0x16 0x0>; 1095 #dma-cells = <3>; 1096 status = "disabled"; 1097 }; 1098 1099 qupv3_id_0: geniqup@4ac0000 { 1100 compatible = "qcom,geni-se-qup"; 1101 reg = <0x0 0x04ac0000 0x0 0x2000>; 1102 clock-names = "m-ahb", "s-ahb"; 1103 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1104 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1105 iommus = <&apps_smmu 0x3 0x0>; 1106 #address-cells = <2>; 1107 #size-cells = <2>; 1108 ranges; 1109 status = "disabled"; 1110 1111 i2c0: i2c@4a80000 { 1112 compatible = "qcom,geni-i2c"; 1113 reg = <0x0 0x04a80000 0x0 0x4000>; 1114 clock-names = "se"; 1115 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1116 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1117 pinctrl-names = "default"; 1118 pinctrl-0 = <&qup_i2c0_default>; 1119 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1120 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1121 dma-names = "tx", "rx"; 1122 #address-cells = <1>; 1123 #size-cells = <0>; 1124 status = "disabled"; 1125 }; 1126 1127 spi0: spi@4a80000 { 1128 compatible = "qcom,geni-spi"; 1129 reg = <0x0 0x04a80000 0x0 0x4000>; 1130 clock-names = "se"; 1131 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1132 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1133 pinctrl-names = "default"; 1134 pinctrl-0 = <&qup_spi0_default>; 1135 power-domains = <&rpmpd SM6375_VDDCX>; 1136 operating-points-v2 = <&qup_opp_table>; 1137 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1138 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1139 dma-names = "tx", "rx"; 1140 #address-cells = <1>; 1141 #size-cells = <0>; 1142 status = "disabled"; 1143 }; 1144 1145 i2c1: i2c@4a84000 { 1146 compatible = "qcom,geni-i2c"; 1147 reg = <0x0 0x04a84000 0x0 0x4000>; 1148 clock-names = "se"; 1149 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1150 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1151 pinctrl-names = "default"; 1152 pinctrl-0 = <&qup_i2c1_default>; 1153 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1154 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1155 dma-names = "tx", "rx"; 1156 #address-cells = <1>; 1157 #size-cells = <0>; 1158 status = "disabled"; 1159 }; 1160 1161 spi1: spi@4a84000 { 1162 compatible = "qcom,geni-spi"; 1163 reg = <0x0 0x04a84000 0x0 0x4000>; 1164 clock-names = "se"; 1165 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1166 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1167 power-domains = <&rpmpd SM6375_VDDCX>; 1168 operating-points-v2 = <&qup_opp_table>; 1169 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1170 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1171 dma-names = "tx", "rx"; 1172 #address-cells = <1>; 1173 #size-cells = <0>; 1174 status = "disabled"; 1175 }; 1176 1177 uart1: serial@4a84000 { 1178 compatible = "qcom,geni-uart"; 1179 reg = <0x0 0x04a84000 0x0 0x4000>; 1180 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1181 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1182 clock-names = "se"; 1183 power-domains = <&rpmpd SM6375_VDDCX>; 1184 operating-points-v2 = <&qup_opp_table>; 1185 pinctrl-0 = <&qup_uart1_default>; 1186 pinctrl-names = "default"; 1187 status = "disabled"; 1188 }; 1189 1190 i2c2: i2c@4a88000 { 1191 compatible = "qcom,geni-i2c"; 1192 reg = <0x0 0x04a88000 0x0 0x4000>; 1193 clock-names = "se"; 1194 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1195 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1196 pinctrl-names = "default"; 1197 pinctrl-0 = <&qup_i2c2_default>; 1198 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1199 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1200 dma-names = "tx", "rx"; 1201 #address-cells = <1>; 1202 #size-cells = <0>; 1203 status = "disabled"; 1204 }; 1205 1206 spi2: spi@4a88000 { 1207 compatible = "qcom,geni-spi"; 1208 reg = <0x0 0x04a88000 0x0 0x4000>; 1209 clock-names = "se"; 1210 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1211 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1212 power-domains = <&rpmpd SM6375_VDDCX>; 1213 operating-points-v2 = <&qup_opp_table>; 1214 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1215 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1216 dma-names = "tx", "rx"; 1217 #address-cells = <1>; 1218 #size-cells = <0>; 1219 status = "disabled"; 1220 }; 1221 1222 /* 1223 * As per GCC, QUP3/4/5/11 also exist, but are not even defined downstream. 1224 * There is a comment in the included DTSI of another SoC saying that they 1225 * are not "bolled out" (probably meaning not routed to solder balls) 1226 * TLMM driver however, suggests there are as many as 15 QUPs in total! 1227 * Most of which don't even have pin configurations for.. Sad stuff! 1228 */ 1229 }; 1230 1231 gpi_dma1: dma-controller@4c00000 { 1232 compatible = "qcom,sm6375-gpi-dma", "qcom,sm6350-gpi-dma"; 1233 reg = <0 0x04c00000 0 0x60000>; 1234 interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>, 1236 <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>, 1240 <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH>, 1241 <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH>, 1242 <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>, 1243 <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>; 1244 dma-channels = <10>; 1245 dma-channel-mask = <0x1f>; 1246 iommus = <&apps_smmu 0xd6 0x0>; 1247 #dma-cells = <3>; 1248 status = "disabled"; 1249 }; 1250 1251 qupv3_id_1: geniqup@4cc0000 { 1252 compatible = "qcom,geni-se-qup"; 1253 reg = <0x0 0x04cc0000 0x0 0x2000>; 1254 clock-names = "m-ahb", "s-ahb"; 1255 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1256 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1257 iommus = <&apps_smmu 0xc3 0x0>; 1258 #address-cells = <2>; 1259 #size-cells = <2>; 1260 ranges; 1261 status = "disabled"; 1262 1263 i2c6: i2c@4c80000 { 1264 compatible = "qcom,geni-i2c"; 1265 reg = <0x0 0x04c80000 0x0 0x4000>; 1266 clock-names = "se"; 1267 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1268 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>; 1269 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1270 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1271 dma-names = "tx", "rx"; 1272 #address-cells = <1>; 1273 #size-cells = <0>; 1274 status = "disabled"; 1275 }; 1276 1277 spi6: spi@4c80000 { 1278 compatible = "qcom,geni-spi"; 1279 reg = <0x0 0x04c80000 0x0 0x4000>; 1280 clock-names = "se"; 1281 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1282 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>; 1283 power-domains = <&rpmpd SM6375_VDDCX>; 1284 operating-points-v2 = <&qup_opp_table>; 1285 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1286 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1287 dma-names = "tx", "rx"; 1288 #address-cells = <1>; 1289 #size-cells = <0>; 1290 status = "disabled"; 1291 }; 1292 1293 i2c7: i2c@4c84000 { 1294 compatible = "qcom,geni-i2c"; 1295 reg = <0x0 0x04c84000 0x0 0x4000>; 1296 clock-names = "se"; 1297 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1298 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 1299 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1300 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1301 dma-names = "tx", "rx"; 1302 #address-cells = <1>; 1303 #size-cells = <0>; 1304 status = "disabled"; 1305 }; 1306 1307 spi7: spi@4c84000 { 1308 compatible = "qcom,geni-spi"; 1309 reg = <0x0 0x04c84000 0x0 0x4000>; 1310 clock-names = "se"; 1311 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1312 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 1313 power-domains = <&rpmpd SM6375_VDDCX>; 1314 operating-points-v2 = <&qup_opp_table>; 1315 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1316 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1317 dma-names = "tx", "rx"; 1318 #address-cells = <1>; 1319 #size-cells = <0>; 1320 status = "disabled"; 1321 }; 1322 1323 i2c8: i2c@4c88000 { 1324 compatible = "qcom,geni-i2c"; 1325 reg = <0x0 0x04c88000 0x0 0x4000>; 1326 clock-names = "se"; 1327 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1328 interrupts = <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 1329 pinctrl-names = "default"; 1330 pinctrl-0 = <&qup_i2c8_default>; 1331 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1332 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1333 dma-names = "tx", "rx"; 1334 #address-cells = <1>; 1335 #size-cells = <0>; 1336 status = "disabled"; 1337 }; 1338 1339 spi8: spi@4c88000 { 1340 compatible = "qcom,geni-spi"; 1341 reg = <0x0 0x04c88000 0x0 0x4000>; 1342 clock-names = "se"; 1343 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1344 interrupts = <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 1345 power-domains = <&rpmpd SM6375_VDDCX>; 1346 operating-points-v2 = <&qup_opp_table>; 1347 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1348 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1349 dma-names = "tx", "rx"; 1350 #address-cells = <1>; 1351 #size-cells = <0>; 1352 status = "disabled"; 1353 }; 1354 1355 i2c9: i2c@4c8c000 { 1356 compatible = "qcom,geni-i2c"; 1357 reg = <0x0 0x04c8c000 0x0 0x4000>; 1358 clock-names = "se"; 1359 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1360 interrupts = <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>; 1361 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1362 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1363 dma-names = "tx", "rx"; 1364 #address-cells = <1>; 1365 #size-cells = <0>; 1366 status = "disabled"; 1367 }; 1368 1369 spi9: spi@4c8c000 { 1370 compatible = "qcom,geni-spi"; 1371 reg = <0x0 0x04c8c000 0x0 0x4000>; 1372 clock-names = "se"; 1373 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1374 interrupts = <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>; 1375 power-domains = <&rpmpd SM6375_VDDCX>; 1376 operating-points-v2 = <&qup_opp_table>; 1377 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1378 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1379 dma-names = "tx", "rx"; 1380 #address-cells = <1>; 1381 #size-cells = <0>; 1382 status = "disabled"; 1383 }; 1384 1385 i2c10: i2c@4c90000 { 1386 compatible = "qcom,geni-i2c"; 1387 reg = <0x0 0x04c90000 0x0 0x4000>; 1388 clock-names = "se"; 1389 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1390 interrupts = <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>; 1391 pinctrl-names = "default"; 1392 pinctrl-0 = <&qup_i2c10_default>; 1393 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1394 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1395 dma-names = "tx", "rx"; 1396 #address-cells = <1>; 1397 #size-cells = <0>; 1398 status = "disabled"; 1399 }; 1400 1401 spi10: spi@4c90000 { 1402 compatible = "qcom,geni-spi"; 1403 reg = <0x0 0x04c90000 0x0 0x4000>; 1404 clock-names = "se"; 1405 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1406 interrupts = <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>; 1407 power-domains = <&rpmpd SM6375_VDDCX>; 1408 operating-points-v2 = <&qup_opp_table>; 1409 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1410 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1411 dma-names = "tx", "rx"; 1412 #address-cells = <1>; 1413 #size-cells = <0>; 1414 status = "disabled"; 1415 }; 1416 }; 1417 1418 usb_1: usb@4ef8800 { 1419 compatible = "qcom,sm6375-dwc3", "qcom,dwc3"; 1420 reg = <0 0x04ef8800 0 0x400>; 1421 1422 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1423 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1424 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 1425 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1426 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1427 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 1428 clock-names = "cfg_noc", 1429 "core", 1430 "iface", 1431 "sleep", 1432 "mock_utmi", 1433 "xo"; 1434 1435 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1436 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1437 assigned-clock-rates = <19200000>, <133333333>; 1438 1439 interrupts-extended = <&intc GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 1440 <&intc GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1441 <&mpm 94 IRQ_TYPE_EDGE_BOTH>, 1442 <&mpm 93 IRQ_TYPE_EDGE_BOTH>, 1443 <&mpm 12 IRQ_TYPE_LEVEL_HIGH>; 1444 interrupt-names = "pwr_event", 1445 "hs_phy_irq", 1446 "dp_hs_phy_irq", 1447 "dm_hs_phy_irq", 1448 "ss_phy_irq"; 1449 1450 power-domains = <&gcc USB30_PRIM_GDSC>; 1451 1452 resets = <&gcc GCC_USB30_PRIM_BCR>; 1453 1454 /* 1455 * This property is there to allow USB2 to work, as 1456 * USB3 is not implemented yet - (re)move it when 1457 * proper support is in place. 1458 */ 1459 qcom,select-utmi-as-pipe-clk; 1460 1461 #address-cells = <2>; 1462 #size-cells = <2>; 1463 ranges; 1464 1465 status = "disabled"; 1466 1467 usb_1_dwc3: usb@4e00000 { 1468 compatible = "snps,dwc3"; 1469 reg = <0 0x04e00000 0 0xcd00>; 1470 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1471 maximum-speed = "high-speed"; 1472 phys = <&usb_1_hsphy>; 1473 phy-names = "usb2-phy"; 1474 iommus = <&apps_smmu 0xe0 0x0>; 1475 1476 /* Yes, this impl *does* have an unfunny number of quirks.. */ 1477 snps,hird-threshold = /bits/ 8 <0x10>; 1478 snps,usb2-gadget-lpm-disable; 1479 snps,dis_u2_susphy_quirk; 1480 snps,is-utmi-l1-suspend; 1481 snps,dis-u1-entry-quirk; 1482 snps,dis-u2-entry-quirk; 1483 snps,usb3_lpm_capable; 1484 snps,has-lpm-erratum; 1485 tx-fifo-resize; 1486 }; 1487 }; 1488 1489 adreno_smmu: iommu@5940000 { 1490 compatible = "qcom,sm6375-smmu-v2", "qcom,smmu-v2"; 1491 reg = <0 0x05940000 0 0x10000>; 1492 #iommu-cells = <1>; 1493 #global-interrupts = <2>; 1494 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, 1495 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, 1496 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, 1497 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 1498 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, 1499 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, 1500 <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, 1501 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 1502 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, 1503 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>; 1504 1505 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 1506 clock-names = "bus"; 1507 1508 power-domains = <&gpucc GPU_CX_GDSC>; 1509 }; 1510 1511 gpucc: clock-controller@5990000 { 1512 compatible = "qcom,sm6375-gpucc"; 1513 reg = <0 0x05990000 0 0x9000>; 1514 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1515 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1516 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, 1517 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 1518 power-domains = <&rpmpd SM6375_VDDGX>; 1519 required-opps = <&rpmpd_opp_low_svs>; 1520 #clock-cells = <1>; 1521 #reset-cells = <1>; 1522 #power-domain-cells = <1>; 1523 }; 1524 1525 remoteproc_mss: remoteproc@6080000 { 1526 compatible = "qcom,sm6375-mpss-pas"; 1527 reg = <0x0 0x06080000 0x0 0x10000>; 1528 1529 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>, 1530 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 1531 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 1532 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 1533 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 1534 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 1535 interrupt-names = "wdog", 1536 "fatal", 1537 "ready", 1538 "handover", 1539 "stop-ack", 1540 "shutdown-ack"; 1541 1542 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1543 clock-names = "xo"; 1544 1545 power-domains = <&rpmpd SM6375_VDDCX>; 1546 power-domain-names = "cx"; 1547 1548 memory-region = <&pil_mpss_wlan_mem>; 1549 1550 qcom,smem-states = <&smp2p_modem_out 0>; 1551 qcom,smem-state-names = "stop"; 1552 1553 status = "disabled"; 1554 1555 glink-edge { 1556 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1557 IPCC_MPROC_SIGNAL_GLINK_QMP 1558 IRQ_TYPE_EDGE_RISING>; 1559 mboxes = <&ipcc IPCC_CLIENT_MPSS 1560 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1561 label = "modem"; 1562 qcom,remote-pid = <1>; 1563 }; 1564 }; 1565 1566 remoteproc_adsp: remoteproc@a400000 { 1567 compatible = "qcom,sm6375-adsp-pas"; 1568 reg = <0 0x0a400000 0 0x10000>; 1569 1570 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>, 1571 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 1572 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 1573 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 1574 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 1575 interrupt-names = "wdog", "fatal", "ready", 1576 "handover", "stop-ack"; 1577 1578 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1579 clock-names = "xo"; 1580 1581 power-domains = <&rpmpd SM6375_VDD_LPI_CX>, 1582 <&rpmpd SM6375_VDD_LPI_MX>; 1583 power-domain-names = "lcx", "lmx"; 1584 1585 memory-region = <&pil_adsp_mem>; 1586 1587 qcom,smem-states = <&smp2p_adsp_out 0>; 1588 qcom,smem-state-names = "stop"; 1589 1590 status = "disabled"; 1591 1592 glink-edge { 1593 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 1594 IPCC_MPROC_SIGNAL_GLINK_QMP 1595 IRQ_TYPE_EDGE_RISING>; 1596 mboxes = <&ipcc IPCC_CLIENT_LPASS 1597 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1598 1599 label = "lpass"; 1600 qcom,remote-pid = <2>; 1601 }; 1602 }; 1603 1604 remoteproc_cdsp: remoteproc@b300000 { 1605 compatible = "qcom,sm6375-cdsp-pas"; 1606 reg = <0x0 0x0b300000 0x0 0x10000>; 1607 1608 interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, 1609 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 1610 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 1611 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 1612 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 1613 interrupt-names = "wdog", "fatal", "ready", 1614 "handover", "stop-ack"; 1615 1616 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1617 clock-names = "xo"; 1618 1619 power-domains = <&rpmpd SM6375_VDDCX>; 1620 power-domain-names = "cx"; 1621 1622 memory-region = <&pil_cdsp_mem>; 1623 1624 qcom,smem-states = <&smp2p_cdsp_out 0>; 1625 qcom,smem-state-names = "stop"; 1626 1627 status = "disabled"; 1628 1629 glink-edge { 1630 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 1631 IPCC_MPROC_SIGNAL_GLINK_QMP 1632 IRQ_TYPE_EDGE_RISING>; 1633 mboxes = <&ipcc IPCC_CLIENT_CDSP 1634 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1635 label = "cdsp"; 1636 qcom,remote-pid = <5>; 1637 }; 1638 }; 1639 1640 sram@c125000 { 1641 compatible = "qcom,sm6375-imem", "syscon", "simple-mfd"; 1642 reg = <0 0x0c125000 0 0x1000>; 1643 ranges = <0 0 0x0c125000 0x1000>; 1644 1645 #address-cells = <1>; 1646 #size-cells = <1>; 1647 1648 pil-reloc@94c { 1649 compatible = "qcom,pil-reloc-info"; 1650 reg = <0x94c 0xc8>; 1651 }; 1652 }; 1653 1654 apps_smmu: iommu@c600000 { 1655 compatible = "qcom,sm6375-smmu-500", "arm,mmu-500"; 1656 reg = <0 0x0c600000 0 0x100000>; 1657 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 1658 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 1659 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 1660 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 1661 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 1662 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1663 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1664 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1665 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1666 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1667 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1668 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1669 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1670 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1671 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1672 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1673 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1674 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1675 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1676 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1677 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1678 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1679 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1680 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1681 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1682 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1683 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1684 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1685 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1686 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1687 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1688 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1689 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1690 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1691 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1692 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1693 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1694 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1695 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1696 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1697 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 1698 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 1699 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1700 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1701 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 1702 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1703 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1704 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1705 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1706 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 1707 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 1708 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 1709 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 1710 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1711 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1712 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1713 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1714 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1715 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1716 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1717 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1718 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1719 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1720 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1721 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1722 1723 power-domains = <&gcc HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC>, 1724 <&gcc HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC>, 1725 <&gcc HLOS1_VOTE_TURING_MMU_TBU0_GDSC>; 1726 #global-interrupts = <1>; 1727 #iommu-cells = <2>; 1728 }; 1729 1730 wifi: wifi@c800000 { 1731 compatible = "qcom,wcn3990-wifi"; 1732 reg = <0 0x0c800000 0 0x800000>; 1733 reg-names = "membase"; 1734 memory-region = <&pil_wlan_mem>; 1735 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 1736 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 1737 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 1738 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 1739 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 1740 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, 1741 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 1742 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 1743 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 1744 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 1745 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 1746 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1747 iommus = <&apps_smmu 0x80 0x1>; 1748 qcom,msa-fixed-perm; 1749 status = "disabled"; 1750 }; 1751 1752 intc: interrupt-controller@f200000 { 1753 compatible = "arm,gic-v3"; 1754 reg = <0x0 0x0f200000 0x0 0x10000>, /* GICD */ 1755 <0x0 0x0f240000 0x0 0x100000>; /* GICR * 8 */ 1756 interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>; 1757 #redistributor-regions = <1>; 1758 #interrupt-cells = <3>; 1759 redistributor-stride = <0 0x20000>; 1760 interrupt-controller; 1761 }; 1762 1763 timer@f420000 { 1764 compatible = "arm,armv7-timer-mem"; 1765 reg = <0 0x0f420000 0 0x1000>; 1766 ranges = <0 0 0 0x20000000>; 1767 #address-cells = <1>; 1768 #size-cells = <1>; 1769 1770 frame@f421000 { 1771 reg = <0x0f421000 0x1000>, <0x0f422000 0x1000>; 1772 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1773 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1774 frame-number = <0>; 1775 }; 1776 1777 frame@f423000 { 1778 reg = <0x0f243000 0x1000>; 1779 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1780 frame-number = <1>; 1781 status = "disabled"; 1782 }; 1783 1784 frame@f425000 { 1785 reg = <0x0f425000 0x1000>; 1786 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1787 frame-number = <2>; 1788 status = "disabled"; 1789 }; 1790 1791 frame@f427000 { 1792 reg = <0x0f427000 0x1000>; 1793 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1794 frame-number = <3>; 1795 status = "disabled"; 1796 }; 1797 1798 frame@f429000 { 1799 reg = <0x0f429000 0x1000>; 1800 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1801 frame-number = <4>; 1802 status = "disabled"; 1803 }; 1804 1805 frame@f42b000 { 1806 reg = <0x0f42b000 0x1000>; 1807 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1808 frame-number = <5>; 1809 status = "disabled"; 1810 }; 1811 1812 frame@f42d000 { 1813 reg = <0x0f42d000 0x1000>; 1814 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1815 frame-number = <6>; 1816 status = "disabled"; 1817 }; 1818 }; 1819 1820 cpucp_l3: interconnect@fd90000 { 1821 compatible = "qcom,sm6375-cpucp-l3", "qcom,epss-l3"; 1822 reg = <0 0x0fd90000 0 0x1000>; 1823 1824 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; 1825 clock-names = "xo", "alternate"; 1826 #interconnect-cells = <1>; 1827 }; 1828 1829 cpufreq_hw: cpufreq@fd91000 { 1830 compatible = "qcom,sm6375-cpufreq-epss", "qcom,cpufreq-epss"; 1831 reg = <0 0x0fd91000 0 0x1000>, <0 0x0fd92000 0 0x1000>; 1832 reg-names = "freq-domain0", "freq-domain1"; 1833 1834 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; 1835 clock-names = "xo", "alternate"; 1836 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1837 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1838 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1"; 1839 #freq-domain-cells = <1>; 1840 #clock-cells = <1>; 1841 }; 1842 }; 1843 1844 thermal-zones { 1845 mapss0-thermal { 1846 thermal-sensors = <&tsens0 0>; 1847 1848 trips { 1849 mapss0_alert0: trip-point0 { 1850 temperature = <90000>; 1851 hysteresis = <2000>; 1852 type = "passive"; 1853 }; 1854 1855 mapss0_alert1: trip-point1 { 1856 temperature = <95000>; 1857 hysteresis = <2000>; 1858 type = "passive"; 1859 }; 1860 1861 mapss0_crit: mapss-crit { 1862 temperature = <110000>; 1863 hysteresis = <1000>; 1864 type = "critical"; 1865 }; 1866 }; 1867 }; 1868 1869 cpu0-thermal { 1870 thermal-sensors = <&tsens0 1>; 1871 1872 trips { 1873 cpu0_alert0: trip-point0 { 1874 temperature = <90000>; 1875 hysteresis = <2000>; 1876 type = "passive"; 1877 }; 1878 1879 cpu0_alert1: trip-point1 { 1880 temperature = <95000>; 1881 hysteresis = <2000>; 1882 type = "passive"; 1883 }; 1884 1885 cpu0_crit: cpu-crit { 1886 temperature = <110000>; 1887 hysteresis = <1000>; 1888 type = "critical"; 1889 }; 1890 }; 1891 }; 1892 1893 cpu1-thermal { 1894 thermal-sensors = <&tsens0 2>; 1895 1896 trips { 1897 cpu1_alert0: trip-point0 { 1898 temperature = <90000>; 1899 hysteresis = <2000>; 1900 type = "passive"; 1901 }; 1902 1903 cpu1_alert1: trip-point1 { 1904 temperature = <95000>; 1905 hysteresis = <2000>; 1906 type = "passive"; 1907 }; 1908 1909 cpu1_crit: cpu-crit { 1910 temperature = <110000>; 1911 hysteresis = <1000>; 1912 type = "critical"; 1913 }; 1914 }; 1915 }; 1916 1917 cpu2-thermal { 1918 thermal-sensors = <&tsens0 3>; 1919 1920 trips { 1921 cpu2_alert0: trip-point0 { 1922 temperature = <90000>; 1923 hysteresis = <2000>; 1924 type = "passive"; 1925 }; 1926 1927 cpu2_alert1: trip-point1 { 1928 temperature = <95000>; 1929 hysteresis = <2000>; 1930 type = "passive"; 1931 }; 1932 1933 cpu2_crit: cpu-crit { 1934 temperature = <110000>; 1935 hysteresis = <1000>; 1936 type = "critical"; 1937 }; 1938 }; 1939 }; 1940 1941 cpu3-thermal { 1942 thermal-sensors = <&tsens0 4>; 1943 1944 trips { 1945 cpu3_alert0: trip-point0 { 1946 temperature = <90000>; 1947 hysteresis = <2000>; 1948 type = "passive"; 1949 }; 1950 1951 cpu3_alert1: trip-point1 { 1952 temperature = <95000>; 1953 hysteresis = <2000>; 1954 type = "passive"; 1955 }; 1956 1957 cpu3_crit: cpu-crit { 1958 temperature = <110000>; 1959 hysteresis = <1000>; 1960 type = "critical"; 1961 }; 1962 }; 1963 }; 1964 1965 cpu4-thermal { 1966 thermal-sensors = <&tsens0 5>; 1967 1968 trips { 1969 cpu4_alert0: trip-point0 { 1970 temperature = <90000>; 1971 hysteresis = <2000>; 1972 type = "passive"; 1973 }; 1974 1975 cpu4_alert1: trip-point1 { 1976 temperature = <95000>; 1977 hysteresis = <2000>; 1978 type = "passive"; 1979 }; 1980 1981 cpu4_crit: cpu-crit { 1982 temperature = <110000>; 1983 hysteresis = <1000>; 1984 type = "critical"; 1985 }; 1986 }; 1987 }; 1988 1989 cpu5-thermal { 1990 thermal-sensors = <&tsens0 6>; 1991 1992 trips { 1993 cpu5_alert0: trip-point0 { 1994 temperature = <90000>; 1995 hysteresis = <2000>; 1996 type = "passive"; 1997 }; 1998 1999 cpu5_alert1: trip-point1 { 2000 temperature = <95000>; 2001 hysteresis = <2000>; 2002 type = "passive"; 2003 }; 2004 2005 cpu5_crit: cpu-crit { 2006 temperature = <110000>; 2007 hysteresis = <1000>; 2008 type = "critical"; 2009 }; 2010 }; 2011 }; 2012 2013 cluster0-thermal { 2014 thermal-sensors = <&tsens0 7>; 2015 2016 trips { 2017 cluster0_alert0: trip-point0 { 2018 temperature = <90000>; 2019 hysteresis = <2000>; 2020 type = "passive"; 2021 }; 2022 2023 cluster0_alert1: trip-point1 { 2024 temperature = <95000>; 2025 hysteresis = <2000>; 2026 type = "passive"; 2027 }; 2028 2029 cluster0_crit: cpu-crit { 2030 temperature = <110000>; 2031 hysteresis = <1000>; 2032 type = "critical"; 2033 }; 2034 }; 2035 }; 2036 2037 cluster1-thermal { 2038 thermal-sensors = <&tsens0 8>; 2039 2040 trips { 2041 cluster1_alert0: trip-point0 { 2042 temperature = <90000>; 2043 hysteresis = <2000>; 2044 type = "passive"; 2045 }; 2046 2047 cluster1_alert1: trip-point1 { 2048 temperature = <95000>; 2049 hysteresis = <2000>; 2050 type = "passive"; 2051 }; 2052 2053 cluster1_crit: cpu-crit { 2054 temperature = <110000>; 2055 hysteresis = <1000>; 2056 type = "critical"; 2057 }; 2058 }; 2059 }; 2060 2061 cpu6-thermal { 2062 thermal-sensors = <&tsens0 9>; 2063 2064 trips { 2065 cpu6_alert0: trip-point0 { 2066 temperature = <90000>; 2067 hysteresis = <2000>; 2068 type = "passive"; 2069 }; 2070 2071 cpu6_alert1: trip-point1 { 2072 temperature = <95000>; 2073 hysteresis = <2000>; 2074 type = "passive"; 2075 }; 2076 2077 cpu6_crit: cpu-crit { 2078 temperature = <110000>; 2079 hysteresis = <1000>; 2080 type = "critical"; 2081 }; 2082 }; 2083 }; 2084 2085 cpu7-thermal { 2086 thermal-sensors = <&tsens0 10>; 2087 2088 trips { 2089 cpu7_alert0: trip-point0 { 2090 temperature = <90000>; 2091 hysteresis = <2000>; 2092 type = "passive"; 2093 }; 2094 2095 cpu7_alert1: trip-point1 { 2096 temperature = <95000>; 2097 hysteresis = <2000>; 2098 type = "passive"; 2099 }; 2100 2101 cpu7_crit: cpu-crit { 2102 temperature = <110000>; 2103 hysteresis = <1000>; 2104 type = "critical"; 2105 }; 2106 }; 2107 }; 2108 2109 cpu-unk0-thermal { 2110 thermal-sensors = <&tsens0 11>; 2111 2112 trips { 2113 cpu_unk0_alert0: trip-point0 { 2114 temperature = <90000>; 2115 hysteresis = <2000>; 2116 type = "passive"; 2117 }; 2118 2119 cpu_unk0_alert1: trip-point1 { 2120 temperature = <95000>; 2121 hysteresis = <2000>; 2122 type = "passive"; 2123 }; 2124 2125 cpu_unk0_crit: cpu-crit { 2126 temperature = <110000>; 2127 hysteresis = <1000>; 2128 type = "critical"; 2129 }; 2130 }; 2131 }; 2132 2133 cpu-unk1-thermal { 2134 thermal-sensors = <&tsens0 12>; 2135 2136 trips { 2137 cpu_unk1_alert0: trip-point0 { 2138 temperature = <90000>; 2139 hysteresis = <2000>; 2140 type = "passive"; 2141 }; 2142 2143 cpu_unk1_alert1: trip-point1 { 2144 temperature = <95000>; 2145 hysteresis = <2000>; 2146 type = "passive"; 2147 }; 2148 2149 cpu_unk1_crit: cpu-crit { 2150 temperature = <110000>; 2151 hysteresis = <1000>; 2152 type = "critical"; 2153 }; 2154 }; 2155 }; 2156 2157 gpuss0-thermal { 2158 thermal-sensors = <&tsens0 13>; 2159 2160 trips { 2161 gpuss0_alert0: trip-point0 { 2162 temperature = <90000>; 2163 hysteresis = <2000>; 2164 type = "passive"; 2165 }; 2166 2167 gpuss0_alert1: trip-point1 { 2168 temperature = <95000>; 2169 hysteresis = <2000>; 2170 type = "passive"; 2171 }; 2172 2173 gpuss0_crit: gpu-crit { 2174 temperature = <110000>; 2175 hysteresis = <1000>; 2176 type = "critical"; 2177 }; 2178 }; 2179 }; 2180 2181 gpuss1-thermal { 2182 thermal-sensors = <&tsens0 14>; 2183 2184 trips { 2185 gpuss1_alert0: trip-point0 { 2186 temperature = <90000>; 2187 hysteresis = <2000>; 2188 type = "passive"; 2189 }; 2190 2191 gpuss1_alert1: trip-point1 { 2192 temperature = <95000>; 2193 hysteresis = <2000>; 2194 type = "passive"; 2195 }; 2196 2197 gpuss1_crit: gpu-crit { 2198 temperature = <110000>; 2199 hysteresis = <1000>; 2200 type = "critical"; 2201 }; 2202 }; 2203 }; 2204 2205 mapss1-thermal { 2206 thermal-sensors = <&tsens1 0>; 2207 2208 trips { 2209 mapss1_alert0: trip-point0 { 2210 temperature = <90000>; 2211 hysteresis = <2000>; 2212 type = "passive"; 2213 }; 2214 2215 mapss1_alert1: trip-point1 { 2216 temperature = <95000>; 2217 hysteresis = <2000>; 2218 type = "passive"; 2219 }; 2220 2221 mapss1_crit: mapss-crit { 2222 temperature = <110000>; 2223 hysteresis = <1000>; 2224 type = "critical"; 2225 }; 2226 }; 2227 }; 2228 2229 cwlan-thermal { 2230 thermal-sensors = <&tsens1 1>; 2231 2232 trips { 2233 cwlan_alert0: trip-point0 { 2234 temperature = <90000>; 2235 hysteresis = <2000>; 2236 type = "passive"; 2237 }; 2238 2239 cwlan_alert1: trip-point1 { 2240 temperature = <95000>; 2241 hysteresis = <2000>; 2242 type = "passive"; 2243 }; 2244 2245 cwlan_crit: cwlan-crit { 2246 temperature = <110000>; 2247 hysteresis = <1000>; 2248 type = "critical"; 2249 }; 2250 }; 2251 }; 2252 2253 audio-thermal { 2254 thermal-sensors = <&tsens1 2>; 2255 2256 trips { 2257 audio_alert0: trip-point0 { 2258 temperature = <90000>; 2259 hysteresis = <2000>; 2260 type = "passive"; 2261 }; 2262 2263 audio_alert1: trip-point1 { 2264 temperature = <95000>; 2265 hysteresis = <2000>; 2266 type = "passive"; 2267 }; 2268 2269 audio_crit: audio-crit { 2270 temperature = <110000>; 2271 hysteresis = <1000>; 2272 type = "critical"; 2273 }; 2274 }; 2275 }; 2276 2277 ddr-thermal { 2278 thermal-sensors = <&tsens1 3>; 2279 2280 trips { 2281 ddr_alert0: trip-point0 { 2282 temperature = <90000>; 2283 hysteresis = <2000>; 2284 type = "passive"; 2285 }; 2286 2287 ddr_alert1: trip-point1 { 2288 temperature = <95000>; 2289 hysteresis = <2000>; 2290 type = "passive"; 2291 }; 2292 2293 ddr_crit: ddr-crit { 2294 temperature = <110000>; 2295 hysteresis = <1000>; 2296 type = "critical"; 2297 }; 2298 }; 2299 }; 2300 2301 q6hvx-thermal { 2302 thermal-sensors = <&tsens1 4>; 2303 2304 trips { 2305 q6hvx_alert0: trip-point0 { 2306 temperature = <90000>; 2307 hysteresis = <2000>; 2308 type = "passive"; 2309 }; 2310 2311 q6hvx_alert1: trip-point1 { 2312 temperature = <95000>; 2313 hysteresis = <2000>; 2314 type = "passive"; 2315 }; 2316 2317 q6hvx_crit: q6hvx-crit { 2318 temperature = <110000>; 2319 hysteresis = <1000>; 2320 type = "critical"; 2321 }; 2322 }; 2323 }; 2324 2325 camera-thermal { 2326 thermal-sensors = <&tsens1 5>; 2327 2328 trips { 2329 camera_alert0: trip-point0 { 2330 temperature = <90000>; 2331 hysteresis = <2000>; 2332 type = "passive"; 2333 }; 2334 2335 camera_alert1: trip-point1 { 2336 temperature = <95000>; 2337 hysteresis = <2000>; 2338 type = "passive"; 2339 }; 2340 2341 camera_crit: camera-crit { 2342 temperature = <110000>; 2343 hysteresis = <1000>; 2344 type = "critical"; 2345 }; 2346 }; 2347 }; 2348 2349 mdm-core0-thermal { 2350 thermal-sensors = <&tsens1 6>; 2351 2352 trips { 2353 mdm_core0_alert0: trip-point0 { 2354 temperature = <90000>; 2355 hysteresis = <2000>; 2356 type = "passive"; 2357 }; 2358 2359 mdm_core0_alert1: trip-point1 { 2360 temperature = <95000>; 2361 hysteresis = <2000>; 2362 type = "passive"; 2363 }; 2364 2365 mdm_core0_crit: mdm-core0-crit { 2366 temperature = <110000>; 2367 hysteresis = <1000>; 2368 type = "critical"; 2369 }; 2370 }; 2371 }; 2372 2373 mdm-core1-thermal { 2374 thermal-sensors = <&tsens1 7>; 2375 2376 trips { 2377 mdm_core1_alert0: trip-point0 { 2378 temperature = <90000>; 2379 hysteresis = <2000>; 2380 type = "passive"; 2381 }; 2382 2383 mdm_core1_alert1: trip-point1 { 2384 temperature = <95000>; 2385 hysteresis = <2000>; 2386 type = "passive"; 2387 }; 2388 2389 mdm_core1_crit: mdm-core1-crit { 2390 temperature = <110000>; 2391 hysteresis = <1000>; 2392 type = "critical"; 2393 }; 2394 }; 2395 }; 2396 2397 mdm-vec-thermal { 2398 thermal-sensors = <&tsens1 8>; 2399 2400 trips { 2401 mdm_vec_alert0: trip-point0 { 2402 temperature = <90000>; 2403 hysteresis = <2000>; 2404 type = "passive"; 2405 }; 2406 2407 mdm_vec_alert1: trip-point1 { 2408 temperature = <95000>; 2409 hysteresis = <2000>; 2410 type = "passive"; 2411 }; 2412 2413 mdm_vec_crit: mdm-vec-crit { 2414 temperature = <110000>; 2415 hysteresis = <1000>; 2416 type = "critical"; 2417 }; 2418 }; 2419 }; 2420 2421 msm-scl-thermal { 2422 thermal-sensors = <&tsens1 9>; 2423 2424 trips { 2425 msm_scl_alert0: trip-point0 { 2426 temperature = <90000>; 2427 hysteresis = <2000>; 2428 type = "passive"; 2429 }; 2430 2431 msm_scl_alert1: trip-point1 { 2432 temperature = <95000>; 2433 hysteresis = <2000>; 2434 type = "passive"; 2435 }; 2436 2437 msm_scl_crit: msm-scl-crit { 2438 temperature = <110000>; 2439 hysteresis = <1000>; 2440 type = "critical"; 2441 }; 2442 }; 2443 }; 2444 2445 video-thermal { 2446 thermal-sensors = <&tsens1 10>; 2447 2448 trips { 2449 video_alert0: trip-point0 { 2450 temperature = <90000>; 2451 hysteresis = <2000>; 2452 type = "passive"; 2453 }; 2454 2455 video_alert1: trip-point1 { 2456 temperature = <95000>; 2457 hysteresis = <2000>; 2458 type = "passive"; 2459 }; 2460 2461 video_crit: video-crit { 2462 temperature = <110000>; 2463 hysteresis = <1000>; 2464 type = "critical"; 2465 }; 2466 }; 2467 }; 2468 }; 2469 2470 timer { 2471 compatible = "arm,armv8-timer"; 2472 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2473 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2474 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2475 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 2476 }; 2477}; 2478