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/linux/include/uapi/linux/genwqe/
H A Dgenwqe_card.h89 * SLC: Queue Virtual Window Window for accessing into a specific VF
98 /* SLC: Queue Segment */
102 /* SLC: Queue Offset */
106 /* SLC: Queue Configuration */
110 /* SLC: Job Timout/Only accessible for the PF */
116 /* SLC: Queue InitSequence Register */
120 /* SLC: Queue Wrap */
124 /* SLC: Queue Status */
128 /* SLC: Queue Working Time */
132 /* SLC: Queue Error Counts */
[all …]
/linux/rust/zerocopy/src/
H A Dbyte_slice.rs377 let slc = v.as_slice(); in prove_split_at_unchecked() localVariable
379 kani::assume(mid <= slc.len()); in prove_split_at_unchecked()
380 let (l, r) = unsafe { slc.split_at_unchecked(mid) }; in prove_split_at_unchecked()
381 assert_eq!(l.len() + r.len(), slc.len()); in prove_split_at_unchecked()
383 let slc: *const _ = slc; in prove_split_at_unchecked() localVariable
387 assert_eq!(slc.cast::<u8>(), l.cast::<u8>()); in prove_split_at_unchecked()
388 assert_eq!(unsafe { slc.cast::<u8>().add(mid) }, r.cast::<u8>()); in prove_split_at_unchecked()
391 let slc = v.as_mut_slice(); in prove_split_at_unchecked() localVariable
392 let len = slc.len(); in prove_split_at_unchecked()
394 kani::assume(mid <= slc.len()); in prove_split_at_unchecked()
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/linux/Documentation/devicetree/bindings/mtd/
H A Dlpc32xx-slc.txt1 NXP LPC32xx SoC NAND SLC controller
4 - compatible: "nxp,lpc3220-slc"
27 slc: flash@20020000 {
28 compatible = "nxp,lpc3220-slc";
/linux/drivers/gpu/drm/amd/amdkfd/
H A Dcwsr_trap_handler_gfx8.asm352 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
353 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256
354 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2
355 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3
407 buffer_store_dwordx2 v[0:1], v2, s_save_buf_rsrc0, s_save_mem_offset offen:1 glc:1 slc:1
450 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
451 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256
452 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2
453 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3
547 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1
[all …]
/linux/drivers/gpu/drm/imagination/
H A Dpvr_rogue_defs.h147 * If the size of the SLC is less than this value then the TPU bypasses the SLC.
152 * If the size of the SLC is bigger than this value then the TCU must not be
153 * bypassed in the SLC.
H A Dpvr_rogue_meta.h231 * SLC caching strategy in S7 and volcanic is emitted through the segment MMU.
233 * CACHED in the SLC.
267 * - SLC uncached, META cached, FW base address 0x70000000
268 * - SLC uncached, META uncached, FW base address 0xF0000000
269 * - SLC cached, META cached, FW base address 0x10000000
270 * - SLC cached, META uncached, FW base address 0x90000000
277 * For non-VIVT SLCs the cacheability of the FW data in the SLC is selected in
/linux/tools/perf/pmu-events/arch/arm64/arm/cmn/sys/
H A Dcmn.json22 "BriefDescription": "Counts total allocations in HN SLC (all cache line allocations to SLC).",
78 "BriefDescription": "Counts number of SLC evictions (dirty only).",
86 "BriefDescription": "Counts number of SLC fills to an invalid way.",
/linux/drivers/mtd/nand/raw/
H A Dlpc32xx_slc.c3 * NXP LPC32XX NAND SLC driver
33 * SLC NAND controller register offsets
73 #define SLCSTAT_SLC_FIFO (1 << 1) /* SLC FIFO has data bit */
240 /* Reset SLC controller */ in lpc32xx_nand_setup()
250 /* Get base clock for SLC block */ in lpc32xx_nand_setup()
325 * Prepares SLC for transfers with H/W ECC enabled
742 host->dma_chan = dma_request_channel(mask, host->pdata->dma_filter, "nand-slc"); in lpc32xx_nand_dma_setup()
905 /* NAND callbacks for LPC32xx SLC hardware */ in lpc32xx_nand_probe()
1014 { .compatible = "nxp,lpc3220-slc" },
1035 MODULE_DESCRIPTION("NAND driver for the NXP LPC32XX SLC controller");
H A DKconfig141 tristate "NXP LPC32xx SLC NAND controller"
145 Enables support for NXP's LPC32XX SLC (i.e. for Single Level Cell
150 by the SLC NAND controller.
H A Dnand_hynix.c380 * expose a valid JEDEC ID. SLC NANDs don't require read-retry. in hynix_nand_rr_init()
618 * Exclude all SLC NANDs from this advanced detection scheme. in hynix_nand_decode_id()
620 * appear that even SLC NANDs could fall in this extended ID scheme. in hynix_nand_decode_id()
621 * If that the case rework the test to let SLC NANDs go through the in hynix_nand_decode_id()
H A Dnand_esmt.c45 * It is known that some ESMT SLC NANDs have been shipped in esmt_nand_init()
H A Dnand_amd.c40 * According to the datasheet of some Cypress SLC NANDs, in amd_nand_init()
/linux/drivers/crypto/cavium/nitrox/
H A Dnitrox_reqmgr.c474 sr->instr.slc.value[0] = 0; in nitrox_process_se_request()
475 sr->instr.slc.s.ssz = sr->out.sgmap_cnt; in nitrox_process_se_request()
476 sr->instr.slc.bev[0] = cpu_to_be64(sr->instr.slc.value[0]); in nitrox_process_se_request()
479 sr->instr.slc.s.rptr = cpu_to_be64(sr->out.sgcomp_dma); in nitrox_process_se_request()
/linux/include/linux/mtd/
H A Dlpc32xx_slc.h3 * Platform data for LPC32xx SoC SLC NAND controller
H A Donenand_regs.h102 /* Note: It's actually 0x3f in case of SLC */
115 /* Note: It's actually 0x03 in case of SLC */
/linux/arch/arc/mm/
H A Dcache.c58 "SLC\t\t: %uK, %uB Line%s\n", in read_decode_cache_bcr_arcv2()
550 * SLC is shared between all cores and concurrent aux operations from in slc_op_rgn()
613 * SLC is shared between all cores and concurrent aux operations from in slc_op_line()
927 * 2. caches (L1 and SLC) need to be purged (flush+inv) before setting up IOC,
954 /* Flush + invalidate SLC */ in arc_ioc_setup()
1043 /* Note that SLC disable not formally supported till HS 3.0 */ in arc_cache_init_master()
1060 * In case of IOC (say IOC+SLC case), pointers above could still be set in arc_cache_init_master()
/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/
H A Dll_cache.json4 …ose transactions are either hit in the system level cache or missed in the SLC and are returned fr…
H A Dl1d_cache.json40 …che line data came from outside the immediate cluster of the core, like an SLC in the system inter…
/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/
H A Dll_cache.json4 …ose transactions are either hit in the system level cache or missed in the SLC and are returned fr…
H A Dl1d_cache.json36 …che line data came from outside the immediate cluster of the core, like an SLC in the system inter…
/linux/include/uapi/mtd/
H A Dmtd-abi.h145 #define MTD_NANDFLASH 4 /* SLC NAND */
154 #define MTD_SLC_ON_MLC_EMULATION 0x4000 /* Emulate SLC behavior on MLC NANDs */
/linux/arch/m68k/include/asm/
H A Dmachines.h67 #define SM_4C_SLC 0x04 /* Sun4c SparcStation SLC - Sun 4/20 */
/linux/Documentation/translations/zh_CN/filesystems/
H A Dubifs.rst35 4. 擦除块在经历一定次数的擦写周期后会磨损，通常 SLC NAND 和 NOR 闪存为
/linux/drivers/mtd/ubi/
H A DKconfig25 The default value should be OK for SLC NAND flashes, NOR flashes and
/linux/arch/sparc/kernel/
H A Dcpu.c66 /* Sun4/100, 4/200, SLC */
78 /* SparcStation SLC, SparcStation1 */

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