| /linux/drivers/cpufreq/ |
| H A D | sa1110-cpufreq.c | 8 * 7 - SDRAM auto-power-up failure (rev A0)
10 * SDRAM reads (rev A0, B0, B1)
14 * The SDRAM type can be passed on the command line as cpu_sa1110.sdram=type
144 struct sdram_params *sdram) in sdram_calculate_timing() argument
152 * If SDCLK would invalidate the SDRAM timings, in sdram_calculate_timing()
158 if ((ns_to_cycles(sdram->tck, sd_khz) > 1) || in sdram_calculate_timing()
164 twr = ns_to_cycles(sdram->twr, mem_khz); in sdram_calculate_timing()
167 trp = ns_to_cycles(sdram->trp, mem_khz) - 1; in sdram_calculate_timing()
173 sd->mdcnfg |= sdram->cas_latency << 12; in sdram_calculate_timing()
174 sd->mdcnfg |= sdram->cas_latency << 28; in sdram_calculate_timing()
[all …]
|
| /linux/drivers/edac/ |
| H A D | altera_edac.h | 14 /* SDRAM Controller CtrlCfg Register */
17 /* SDRAM Controller CtrlCfg Register Bit Masks */
25 /* SDRAM Controller Address Width Register */
28 /* SDRAM Controller Address Widths Field Register */
38 /* SDRAM Controller Interface Data Width Register */
41 /* SDRAM Controller Interface Data Width Defines */
45 /* SDRAM Controller DRAM Status Register */
48 /* SDRAM Controller DRAM Status Register Bit Masks */
53 /* SDRAM Controller DRAM IRQ Register */
56 /* SDRAM Controller DRAM IRQ Register Bit Masks */
[all …]
|
| H A D | r82600_edac.c | 33 /* Radisys say "The 82600 integrates a main memory SDRAM controller that
35 * sizes of 64 bit wide (72 bits with ECC) Synchronous DRAM (SDRAM) DIMMs,
39 * is not allowed. The 82600 SDRAM interface operates at the same frequency as
50 #define R82600_DRAMC 0x57 /* Various SDRAM related control bits
53 * 7 SDRAM ISA Hole Enable
58 * 2 SDRAM BIOS Flash Write Enable
59 * 1:0 SDRAM Refresh Rate: 00=Disabled
64 #define R82600_SDRAMC 0x76 /* "SDRAM Control Register"
65 * More SDRAM related control bits
70 * 7:5 Special SDRAM Mode Select
[all …]
|
| /linux/arch/arm/mach-pxa/ |
| H A D | smemc.h | 15 #define MDCNFG (SMEMC_VIRT + 0x00) /* SDRAM Configuration Register 0 */
16 #define MDREFR (SMEMC_VIRT + 0x04) /* SDRAM Refresh Control Register */
21 #define SXLCR (SMEMC_VIRT + 0x18) /* LCR value to be written to SDRAM-Timing Synchronous Flash */
30 #define MDMRS (SMEMC_VIRT + 0x40) /* MRS value to be written to SDRAM */
52 #define MDCNFG_DE0 (1 << 0) /* SDRAM Bank 0 Enable */
53 #define MDCNFG_DE1 (1 << 1) /* SDRAM Bank 1 Enable */
54 #define MDCNFG_DE2 (1 << 16) /* SDRAM Bank 2 Enable */
55 #define MDCNFG_DE3 (1 << 17) /* SDRAM Bank 3 Enable */
58 #define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
59 #define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
[all …]
|
| H A D | sleep.S | 55 @ prepare SDRAM refresh settings
59 @ enable SDRAM self-refresh mode
96 @ prepare SDRAM refresh settings
100 @ enable SDRAM self-refresh mode
107 @ We keep the change-down close to the actual suspend on SDRAM
160 @ external accesses after SDRAM is put in self-refresh mode
166 @ put SDRAM into self-refresh
|
| /linux/include/soc/at91/ |
| H A D | at91sam9_sdramc.h | 8 * SDRAM Controllers (SDRAMC) - System peripherals registers.
15 /* SDRAM Controller (SDRAMC) registers */
16 #define AT91_SDRAMC_MR 0x00 /* SDRAM Controller Mode Register */
26 #define AT91_SDRAMC_TR 0x04 /* SDRAM Controller Refresh Timer Register */
29 #define AT91_SDRAMC_CR 0x08 /* SDRAM Controller Configuration Register */
56 #define AT91_SDRAMC_LPR 0x10 /* SDRAM Controller Low Power Register */
70 #define AT91_SDRAMC_IER 0x14 /* SDRAM Controller Interrupt Enable Register */
71 #define AT91_SDRAMC_IDR 0x18 /* SDRAM Controller Interrupt Disable Register */
72 #define AT91_SDRAMC_IMR 0x1C /* SDRAM Controller Interrupt Mask Register */
73 #define AT91_SDRAMC_ISR 0x20 /* SDRAM Controller Interrupt Status Register */
[all …]
|
| H A D | sama7-ddr.h | 55 #define UDDRC_STAT_SELFREF_TYPE_DIS (0x0 << 4) /* SDRAM is not in Self-refresh */
56 #define UDDRC_STAT_SELFREF_TYPE_PHY (0x1 << 4) /* SDRAM is in Self-refresh, which was caused by PH…
57 #define UDDRC_STAT_SELFREF_TYPE_SW (0x2 << 4) /* SDRAM is in Self-refresh, which was not caused so…
58 #define UDDRC_STAT_SELFREF_TYPE_AUTO (0x3 << 4) /* SDRAM is in Self-refresh, which was caused by A…
|
| /linux/Documentation/devicetree/bindings/arm/altera/ |
| H A D | socfpga-sdram-edac.txt | 1 Altera SOCFPGA SDRAM Error Detection & Correction [EDAC]
2 The EDAC accesses a range of registers in the SDRAM controller.
5 - compatible : should contain "altr,sdram-edac" or "altr,sdram-edac-a10"
7 - interrupts : Should contain the SDRAM ECC IRQ in the
12 compatible = "altr,sdram-edac";
|
| /linux/Documentation/devicetree/bindings/edac/ |
| H A D | aspeed-sdram-edac.txt | 15 - "aspeed,ast2400-sdram-edac"
16 - "aspeed,ast2500-sdram-edac"
17 - "aspeed,ast2600-sdram-edac"
18 - reg: sdram controller register set should be <0x1e6e0000 0x174>
24 edac: sdram@1e6e0000 {
25 compatible = "aspeed,ast2500-sdram-edac";
|
| /linux/drivers/net/usb/ |
| H A D | sr9700.h | 113 /* Tx sdram Write Pointer Address Low */
115 /* Tx sdram Write Pointer Address High */
117 /* Tx sdram Read Pointer Address Low */
119 /* Tx sdram Read Pointer Address High */
121 /* Rx sdram Write Pointer Address Low */
123 /* Rx sdram Write Pointer Address High */
125 /* Rx sdram Read Pointer Address Low */
127 /* Rx sdram Read Pointer Address High */
|
| /linux/drivers/clk/sunxi-ng/ |
| H A D | ccu-sun9i-a80-de.c | 42 static SUNXI_CCU_GATE(dram_fe0_clk, "dram-fe0", "sdram",
44 static SUNXI_CCU_GATE(dram_fe1_clk, "dram-fe1", "sdram",
46 static SUNXI_CCU_GATE(dram_fe2_clk, "dram-fe2", "sdram",
48 static SUNXI_CCU_GATE(dram_deu0_clk, "dram-deu0", "sdram",
50 static SUNXI_CCU_GATE(dram_deu1_clk, "dram-deu1", "sdram",
52 static SUNXI_CCU_GATE(dram_be0_clk, "dram-be0", "sdram",
54 static SUNXI_CCU_GATE(dram_be1_clk, "dram-be1", "sdram",
56 static SUNXI_CCU_GATE(dram_be2_clk, "dram-be2", "sdram",
58 static SUNXI_CCU_GATE(dram_drc0_clk, "dram-drc0", "sdram",
60 static SUNXI_CCU_GATE(dram_drc1_clk, "dram-drc1", "sdram",
|
| /linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | marvell,mvebu-sdram-controller.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/marvell,mvebu-sdram-controller.yaml#
7 title: Marvell MVEBU SDRAM controller
15 const: marvell,armada-xp-sdram-controller
29 compatible = "marvell,armada-xp-sdram-controller";
|
| /linux/drivers/fpga/ |
| H A D | altera-fpga2sdram.c | 3 * FPGA to SDRAM Bridge Driver for Altera SoCFPGA Devices
9 * This driver manages a bridge between an FPGA and the SDRAM used by the ARM
13 * Reconfiguring these ports requires that no SDRAM transactions occur during
14 * reconfiguration. The code reconfiguring the ports cannot run out of SDRAM
15 * nor can the FPGA access the SDRAM during reconfiguration. This driver does
164 MODULE_DESCRIPTION("Altera SoCFPGA FPGA to SDRAM Bridge");
|
| /linux/arch/m68k/include/asm/ |
| H A D | m520xsim.h | 74 * SDRAM configuration registers.
76 #define MCFSIM_SDMR 0xFC0a8000 /* SDRAM Mode/Extended Mode Register */
77 #define MCFSIM_SDCR 0xFC0a8004 /* SDRAM Control Register */
78 #define MCFSIM_SDCFG1 0xFC0a8008 /* SDRAM Configuration Register 1 */
79 #define MCFSIM_SDCFG2 0xFC0a800c /* SDRAM Configuration Register 2 */
80 #define MCFSIM_SDCS0 0xFC0a8110 /* SDRAM Chip Select 0 Configuration */
81 #define MCFSIM_SDCS1 0xFC0a8114 /* SDRAM Chip Select 1 Configuration */
|
| /linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | ralink,rt2880-pinctrl.yaml | 38 enum: [gpio, i2c, spi, uartlite, jtag, mdio, sdram, pci]
57 enum: [i2c, spi, uartlite, jtag, mdio, sdram, pci]
107 const: sdram
111 enum: [sdram]
|
| H A D | ralink,rt305x-pinctrl.yaml | 39 pcm gpio, pcm i2s, pcm uartf, rgmii, sdram, spi, uartf,
59 enum: [i2c, jtag, mdio, rgmii, sdram, spi, uartf, uartlite]
154 const: sdram
158 enum: [sdram]
|
| /linux/drivers/clk/pxa/ |
| H A D | clk-pxa.c | 23 #define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
24 #define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
25 #define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */
26 #define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */
27 #define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */
169 /* Calculate the next MDREFR. If we're slowing down the SDRAM clock in pxa2xx_cpll_change()
182 /* If we're dividing the memory clock by two for the SDRAM clock, this in pxa2xx_cpll_change()
|
| /linux/arch/m68k/coldfire/ |
| H A D | m53xx.c | 61 DEFINE_CLK(0, "sdram.0", 46, MCF_CLK);
99 CLKDEV_INIT("sdram.0", NULL, &__clk_0_46),
122 &__clk_0_46, /* sdram.0 */
268 * SDRAM Timing Parameters
369 * Check to see if the SDRAM has already been initialized in sdramc_init()
373 /* SDRAM chip select initialization */ in sdramc_init()
375 /* Initialize SDRAM chip select */ in sdramc_init()
501 * Check to see if the SDRAM has already been initialized. in clock_pll()
502 * If it has then the SDRAM needs to be put into self refresh in clock_pll()
506 /* Put SDRAM into self refresh mode */ in clock_pll()
[all …]
|
| /linux/arch/sh/drivers/pci/ |
| H A D | pci-sh7751.c | 25 /* check BCR for SDRAM in area */ in __area_sdram_check()
27 printk("PCI: Area %d is not configured for SDRAM. BCR1=0x%lx\n", in __area_sdram_check()
34 /* check BCR2 for 32bit SDRAM interface*/ in __area_sdram_check()
36 printk("PCI: Area %d is not 32 bit SDRAM. BCR2=0x%lx\n", in __area_sdram_check()
141 /* check BCR for SDRAM in specified area */ in sh7751_pci_init()
|
| /linux/arch/powerpc/platforms/52xx/ |
| H A D | mpc52xx_sleep.S | 10 mpc52xx_deep_sleep: /* args r3-r6: SRAM, SDRAM regs, CDM regs, INTR regs */
68 /* put SDRAM into self-refresh */
69 lwz r8, 0x4(r4) /* sdram->ctrl */
89 /* disable SDRAM clock */
|
| /linux/arch/arm/mach-lpc32xx/ |
| H A D | pm.c | 40 * DRAM or regular SDRAM devices. If SDRAM is used in the system, the
41 * SDRAM will still be accessible in direct-run mode. In DDR based systems,
126 * Setup SDRAM self-refresh clock to automatically disable o in lpc32xx_pm_init()
|
| /linux/arch/sh/include/mach-common/mach/ |
| H A D | sh7785lcr.h | 14 * 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM
15 * 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM
19 * 0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use)
|
| /linux/Documentation/driver-api/memory-devices/ |
| H A D | ti-emif.rst | 4 TI EMIF SDRAM Controller Driver
29 SoCs. EMIF is an SDRAM controller that, based on its revision,
30 supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
|
| /linux/arch/arm/mach-imx/ |
| H A D | mx3x.h | 21 * 80000000 256M CSD0 SDRAM/DDR
22 * 90000000 256M CSD1 SDRAM/DDR
29 * FC320000 B8000000 64K NAND, SDRAM, WEIM, M3IF, EMI controllers
127 * NAND, SDRAM, WEIM, M3IF, EMI controllers
|
| /linux/Documentation/devicetree/bindings/memory-controllers/ti/ |
| H A D | emif.txt | 1 * EMIF family of TI SDRAM controllers
3 EMIF - External Memory Interface - is an SDRAM controller used in
57 has capability for generating SDRAM temperature alerts
|