Lines Matching full:sdram

33 /* Radisys say "The 82600 integrates a main memory SDRAM controller that
35  * sizes of 64 bit wide (72 bits with ECC) Synchronous DRAM (SDRAM) DIMMs,
39  * is not allowed. The 82600 SDRAM interface operates at the same frequency as
50 #define R82600_DRAMC	0x57	/* Various SDRAM related control bits
53 				 * 7    SDRAM ISA Hole Enable
58 				 * 2    SDRAM BIOS Flash Write Enable
59 				 * 1:0  SDRAM Refresh Rate: 00=Disabled
64 #define R82600_SDRAMC	0x76	/* "SDRAM Control Register"
65 				 * More SDRAM related control bits
70 				 * 7:5  Special SDRAM Mode Select
122 #define R82600_DRBA	0x60	/* + 0x60..0x63 SDRAM Row Boundary Address
222 	u8 drbar;		/* SDRAM Row Boundary Address Register */  in r82600_init_csrows()
283 	edac_dbg(2, "sdram refresh rate = %#0x\n", sdram_refresh_rate);  in r82600_probe1()