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/linux/Documentation/devicetree/bindings/spi/
H A Drockchip-sfc.yaml76 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
/linux/include/dt-bindings/clock/
H A Drk3036-cru.h49 #define SCLK_SFC 160 macro
H A Drk3128-cru.h67 #define SCLK_SFC 153 macro
H A Drv1108-cru.h30 #define SCLK_SFC 80 macro
H A Drk3368-cru.h72 #define SCLK_SFC 126 macro
H A Drk3308-cru.h65 #define SCLK_SFC 61 macro
H A Dpx30-cru.h60 #define SCLK_SFC 58 macro
H A Drockchip,rv1126-cru.h184 #define SCLK_SFC 118 macro
H A Drockchip,rk3588-cru.h318 #define SCLK_SFC 303 macro
H A Drk3568-cru.h184 #define SCLK_SFC 120 macro
/linux/arch/arm/boot/dts/rockchip/
H A Drv1126.dtsi192 <&cru SCLK_SFC>;
709 assigned-clocks = <&cru SCLK_SFC>;
712 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
H A Drv1108.dtsi540 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
H A Drk3128.dtsi456 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
/linux/drivers/clk/rockchip/
H A Dclk-rk3036.c344 COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_dmyapll_dpll_gpll_xin24_p, 0,
H A Dclk-rk3128.c552 COMPOSITE(SCLK_SFC, "sclk_sfc", mux_sclk_sfc_src_p, 0,
H A Dclk-rv1108.c745 COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_2plls_p, 0,
H A Dclk-rk3368.c585 COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_cpll_gpll_p, 0,
H A Dclk-rv1126.c814 COMPOSITE(SCLK_SFC, "sclk_sfc", mux_cpll_gpll_p, 0,
H A Dclk-rk3568.c793 COMPOSITE_NODIV(SCLK_SFC, "sclk_sfc", sclk_sfc_p, 0,
H A Dclk-rk3308.c523 COMPOSITE(SCLK_SFC, "clk_sfc", mux_dpll_vpll0_vpll1_p, 0,
H A Dclk-px30.c504 COMPOSITE(SCLK_SFC, "clk_sfc", mux_gpll_cpll_p, 0,
H A Dclk-rk3588.c1473 COMPOSITE(SCLK_SFC, "sclk_sfc", gpll_cpll_24m_p, 0,
/linux/arch/arm64/boot/dts/rockchip/
H A Dpx30.dtsi300 <&cru SCLK_SFC>;
1042 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
H A Drk3308.dtsi816 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
H A Drk3588-base.dtsi1865 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;