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Searched full:sclk (Results 1 – 25 of 280) sorted by relevance

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/linux/drivers/clk/ralink/
H A Dclk-mt7621.c134 struct mt7621_gate *sclk) in mt7621_gate_ops_init() argument
145 .parent_names = &sclk->parent_name, in mt7621_gate_ops_init()
147 .name = sclk->name, in mt7621_gate_ops_init()
150 sclk->hw.init = &init; in mt7621_gate_ops_init()
151 return devm_clk_hw_register(dev, &sclk->hw); in mt7621_gate_ops_init()
159 struct mt7621_gate *sclk; in mt7621_register_gates() local
163 sclk = &mt7621_gates[i]; in mt7621_register_gates()
164 sclk->priv = priv; in mt7621_register_gates()
165 ret = mt7621_gate_ops_init(dev, sclk); in mt7621_register_gates()
167 dev_err(dev, "Couldn't register clock %s\n", sclk->name); in mt7621_register_gates()
[all …]
/linux/drivers/clk/
H A Dclk-scmi.c220 static int scmi_clk_ops_init(struct device *dev, struct scmi_clk *sclk, in scmi_clk_ops_init() argument
228 .num_parents = sclk->info->num_parents, in scmi_clk_ops_init()
230 .name = sclk->info->name, in scmi_clk_ops_init()
231 .parent_data = sclk->parent_data, in scmi_clk_ops_init()
234 sclk->hw.init = &init; in scmi_clk_ops_init()
235 ret = devm_clk_hw_register(dev, &sclk->hw); in scmi_clk_ops_init()
239 if (sclk->info->rate_discrete) { in scmi_clk_ops_init()
240 int num_rates = sclk->info->list.num_rates; in scmi_clk_ops_init()
245 min_rate = sclk->info->list.rates[0]; in scmi_clk_ops_init()
246 max_rate = sclk->info->list.rates[num_rates - 1]; in scmi_clk_ops_init()
[all …]
H A Dclk-scpi.c141 struct scpi_clk *sclk, const char *name) in scpi_clk_ops_init() argument
151 sclk->hw.init = &init; in scpi_clk_ops_init()
152 sclk->scpi_ops = get_scpi_ops(); in scpi_clk_ops_init()
155 sclk->info = sclk->scpi_ops->dvfs_get_info(sclk->id); in scpi_clk_ops_init()
156 if (IS_ERR(sclk->info)) in scpi_clk_ops_init()
157 return PTR_ERR(sclk->info); in scpi_clk_ops_init()
159 if (sclk->scpi_ops->clk_get_range(sclk->id, &min, &max) || !max) in scpi_clk_ops_init()
165 ret = devm_clk_hw_register(dev, &sclk->hw); in scpi_clk_ops_init()
167 clk_hw_set_rate_range(&sclk->hw, min, max); in scpi_clk_ops_init()
179 struct scpi_clk *sclk; in scpi_of_clk_src_get() local
[all …]
/linux/drivers/clk/microchip/
H A Dclk-core.c759 /* System mux clock(aka SCLK) */
774 struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw); in sclk_get_rate() local
777 div = (readl(sclk->slew_reg) >> SLEW_SYSDIV_SHIFT) & SLEW_SYSDIV; in sclk_get_rate()
795 struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw); in sclk_set_rate() local
802 spin_lock_irqsave(&sclk->core->reg_lock, flags); in sclk_set_rate()
805 v = readl(sclk->slew_reg); in sclk_set_rate()
811 writel(v, sclk->slew_reg); in sclk_set_rate()
814 err = readl_poll_timeout_atomic(sclk->slew_reg, v, in sclk_set_rate()
817 spin_unlock_irqrestore(&sclk->core->reg_lock, flags); in sclk_set_rate()
824 struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw); in sclk_get_parent() local
[all …]
/linux/drivers/gpu/drm/radeon/
H A Drv730_dpm.c39 RV770_SMC_SCLK_VALUE *sclk) in rv730_populate_sclk_value() argument
106 sclk->sclk_value = cpu_to_be32(engine_clock); in rv730_populate_sclk_value()
107 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv730_populate_sclk_value()
108 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); in rv730_populate_sclk_value()
109 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); in rv730_populate_sclk_value()
110 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(cg_spll_spread_spectrum); in rv730_populate_sclk_value()
111 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(cg_spll_spread_spectrum_2); in rv730_populate_sclk_value()
302 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv730_populate_smc_acpi_state()
303 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); in rv730_populate_smc_acpi_state()
304 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); in rv730_populate_smc_acpi_state()
[all …]
H A Drv770_dpm.c273 a_n = (int)state->medium.sclk * pi->lmp + in rv770_populate_smc_t()
274 (int)state->low.sclk * (R600_AH_DFLT - pi->rlp); in rv770_populate_smc_t()
275 a_d = (int)state->low.sclk * (100 - (int)pi->rlp) + in rv770_populate_smc_t()
276 (int)state->medium.sclk * pi->lmp; in rv770_populate_smc_t()
281 a_n = (int)state->high.sclk * pi->lhp + (int)state->medium.sclk * in rv770_populate_smc_t()
283 a_d = (int)state->medium.sclk * (100 - (int)pi->rmp) + in rv770_populate_smc_t()
284 (int)state->high.sclk * pi->lhp; in rv770_populate_smc_t()
487 RV770_SMC_SCLK_VALUE *sclk) in rv770_populate_sclk_value() argument
557 sclk->sclk_value = cpu_to_be32(engine_clock); in rv770_populate_sclk_value()
558 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv770_populate_sclk_value()
[all …]
H A Dtrinity_dpm.c536 u32 index, u32 sclk) in trinity_set_divider_value() argument
544 sclk, false, &dividers); in trinity_set_divider_value()
554 sclk/2, false, &dividers); in trinity_set_divider_value()
674 trinity_set_divider_value(rdev, index, pl->sclk); in trinity_program_power_level()
921 if (new_ps->levels[new_ps->num_levels - 1].sclk >= in trinity_set_uvd_clock_before_set_eng_clock()
922 current_ps->levels[current_ps->num_levels - 1].sclk) in trinity_set_uvd_clock_before_set_eng_clock()
935 if (new_ps->levels[new_ps->num_levels - 1].sclk < in trinity_set_uvd_clock_after_set_eng_clock()
936 current_ps->levels[current_ps->num_levels - 1].sclk) in trinity_set_uvd_clock_after_set_eng_clock()
1286 static u8 trinity_calculate_vce_wm(struct radeon_device *rdev, u32 sclk) in trinity_calculate_vce_wm() argument
1288 if (sclk < 20000) in trinity_calculate_vce_wm()
[all …]
H A Dsumo_dpm.c345 u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk; in sumo_program_bsp()
348 highest_engine_clock = pi->boost_pl.sclk; in sumo_program_bsp()
409 m_a = asi * ps->levels[i].sclk / 100; in sumo_program_at()
419 m_a = asi * pi->boost_pl.sclk / 100; in sumo_program_at()
553 pl->sclk, false, &dividers); in sumo_program_power_level()
669 pi->boost_pl.sclk = pi->sys_info.boost_sclk; in sumo_patch_boost_state()
788 pi->acpi_pl.sclk, in sumo_program_acpi_power_level()
842 if (new_ps->levels[new_ps->num_levels - 1].sclk >= in sumo_set_uvd_clock_before_set_eng_clock()
843 current_ps->levels[current_ps->num_levels - 1].sclk) in sumo_set_uvd_clock_before_set_eng_clock()
860 if (new_ps->levels[new_ps->num_levels - 1].sclk < in sumo_set_uvd_clock_after_set_eng_clock()
[all …]
H A Dbtc_dpm.c1214 u32 *sclk, u32 *mclk) in btc_skip_blacklist_clocks() argument
1218 if ((sclk == NULL) || (mclk == NULL)) in btc_skip_blacklist_clocks()
1224 if ((btc_blacklist_clocks[i].sclk == *sclk) && in btc_skip_blacklist_clocks()
1231 *sclk = btc_get_valid_sclk(rdev, max_sclk, *sclk + 1); in btc_skip_blacklist_clocks()
1233 if (*sclk < max_sclk) in btc_skip_blacklist_clocks()
1234 btc_skip_blacklist_clocks(rdev, max_sclk, max_mclk, sclk, mclk); in btc_skip_blacklist_clocks()
1244 if ((pl->mclk == 0) || (pl->sclk == 0)) in btc_adjust_clock_combinations()
1247 if (pl->mclk == pl->sclk) in btc_adjust_clock_combinations()
1250 if (pl->mclk > pl->sclk) { in btc_adjust_clock_combinations()
1251 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > rdev->pm.dpm.dyn_state.mclk_sclk_ratio) in btc_adjust_clock_combinations()
[all …]
H A Dkv_dpm.c376 u32 index, u32 sclk) in kv_set_divider_value() argument
383 sclk, false, &dividers); in kv_set_divider_value()
388 pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk); in kv_set_divider_value()
565 if (table->entries[i].clk == pi->boot_pl.sclk) in kv_program_bootup_state()
579 if (table->entries[i].sclk_frequency == pi->boot_pl.sclk) in kv_program_bootup_state()
1536 if ((table->entries[i].clk >= new_ps->levels[0].sclk) || in kv_set_valid_clock_range()
1544 if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk) in kv_set_valid_clock_range()
1550 if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) > in kv_set_valid_clock_range()
1551 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk)) in kv_set_valid_clock_range()
1561 if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk || in kv_set_valid_clock_range()
[all …]
H A Drv740_dpm.c120 RV770_SMC_SCLK_VALUE *sclk) in rv740_populate_sclk_value() argument
175 sclk->sclk_value = cpu_to_be32(engine_clock); in rv740_populate_sclk_value()
176 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv740_populate_sclk_value()
177 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); in rv740_populate_sclk_value()
178 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); in rv740_populate_sclk_value()
179 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(cg_spll_spread_spectrum); in rv740_populate_sclk_value()
180 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(cg_spll_spread_spectrum_2); in rv740_populate_sclk_value()
385 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv740_populate_smc_acpi_state()
386 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); in rv740_populate_smc_acpi_state()
387 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); in rv740_populate_smc_acpi_state()
[all …]
H A Drv6xx_dpm.c439 state->low.sclk; in rv6xx_calculate_engine_speed_stepping_parameters()
441 state->medium.sclk; in rv6xx_calculate_engine_speed_stepping_parameters()
443 state->high.sclk; in rv6xx_calculate_engine_speed_stepping_parameters()
1027 rv6xx_calculate_t(state->low.sclk, in rv6xx_calculate_ap()
1028 state->medium.sclk, in rv6xx_calculate_ap()
1035 rv6xx_calculate_t(state->medium.sclk, in rv6xx_calculate_ap()
1036 state->high.sclk, in rv6xx_calculate_ap()
1426 old_state->low.sclk, in rv6xx_generate_transition_stepping()
1427 new_state->low.sclk, in rv6xx_generate_transition_stepping()
1439 new_state->low.sclk, in rv6xx_generate_low_step()
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dgk104.c68 u32 sclk; in read_pll() local
77 sclk = device->crystal; in read_pll()
81 sclk = read_pll(clk, 0x132020); in read_pll()
85 sclk = read_div(clk, 0, 0x137320, 0x137330); in read_pll()
92 sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140); in read_pll()
101 sclk = (sclk * N) + (((u16)(fN + 4096) * sclk) >> 13); in read_pll()
102 return sclk / (M * P); in read_pll()
121 u32 sclk = read_vco(clk, dsrc + (doff * 4)); in read_div() local
123 return (sclk * 2) / sdiv; in read_div()
149 u32 sclk, sdiv; in read_clk() local
[all …]
H A Dgf100.c67 u32 sclk; in read_pll() local
75 sclk = device->crystal; in read_pll()
79 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrc); in read_pll()
82 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrcref); in read_pll()
88 sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140); in read_pll()
94 return sclk * N / M / P; in read_pll()
102 u32 sclk, sctl, sdiv = 2; in read_div() local
112 sclk = read_vco(clk, dsrc + (doff * 4)); in read_div()
126 return (sclk * 2) / sdiv; in read_div()
138 u32 sclk, sdiv; in read_clk() local
[all …]
H A Dgt215.c64 u32 sctl, sdiv, sclk; in read_clk() local
99 sclk = read_vco(clk, idx); in read_clk()
101 return (sclk * 2) / sdiv; in read_clk()
112 u32 sclk = 0, P = 1, N = 1, M = 1; in read_pll() local
128 sclk = read_clk(clk, 0x00 + idx, false); in read_pll()
131 sclk = read_clk(clk, 0x10 + idx, false); in read_pll()
139 return sclk * N / MP; in read_pll()
191 u32 oclk, sclk, sdiv; in gt215_clk_info() local
207 sclk = read_vco(clk, idx); in gt215_clk_info()
208 sdiv = min((sclk * 2) / khz, (u32)65); in gt215_clk_info()
[all …]
/linux/sound/soc/meson/
H A Daxg-tdm-formatter.c20 struct clk *sclk; member
109 * If sclk is inverted, it means the bit should latched on the in axg_tdm_formatter_enable()
114 ret = clk_set_phase(formatter->sclk, invert ? 0 : 180); in axg_tdm_formatter_enable()
126 ret = clk_prepare_enable(formatter->sclk); in axg_tdm_formatter_enable()
132 clk_disable_unprepare(formatter->sclk); in axg_tdm_formatter_enable()
151 clk_disable_unprepare(formatter->sclk); in axg_tdm_formatter_disable()
208 ret = clk_set_parent(formatter->sclk_sel, ts->iface->sclk); in axg_tdm_formatter_power_up()
298 formatter->sclk = devm_clk_get(dev, "sclk"); in axg_tdm_formatter_probe()
299 if (IS_ERR(formatter->sclk)) in axg_tdm_formatter_probe()
300 return dev_err_probe(dev, PTR_ERR(formatter->sclk), "failed to get sclk\n"); in axg_tdm_formatter_probe()
[all …]
/linux/sound/soc/cirrus/
H A Dep93xx-i2s.c75 struct clk *sclk; member
102 clk_prepare_enable(info->sclk); in ep93xx_i2s_enable()
147 clk_disable_unprepare(info->sclk); in ep93xx_i2s_disable()
318 * EP93xx I2S module can be setup so SCLK / LRCLK value can be in ep93xx_i2s_hw_params()
319 * 32, 64, 128. MCLK / SCLK value can be 2 and 4. in ep93xx_i2s_hw_params()
320 * We set LRCLK equal to `rate' and minimum SCLK / LRCLK in ep93xx_i2s_hw_params()
335 err = clk_set_rate(info->sclk, clk_get_rate(info->mclk) / sdiv); in ep93xx_i2s_hw_params()
339 err = clk_set_rate(info->lrclk, clk_get_rate(info->sclk) / lrdiv); in ep93xx_i2s_hw_params()
455 info->sclk = clk_get(&pdev->dev, "sclk"); in ep93xx_i2s_probe()
456 if (IS_ERR(info->sclk)) { in ep93xx_i2s_probe()
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dnvidia,tegra20-car.yaml46 "^(sclk)|(pll-[cem])$":
51 - nvidia,tegra20-sclk
52 - nvidia,tegra30-sclk
93 sclk {
94 compatible = "nvidia,tegra20-sclk";
/linux/drivers/gpu/drm/armada/
H A Darmada_510.c95 * Armada510 specific SCLK register selection.
96 * This gets called with sclk = NULL to test whether the mode is
97 * supportable, and again with sclk != NULL to set the clocks up for
102 const struct drm_display_mode *mode, uint32_t *sclk) in armada510_crtc_compute_clock() argument
119 if (sclk) { in armada510_crtc_compute_clock()
122 *sclk = res.div | armada510_clk_sels[idx]; in armada510_crtc_compute_clock()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dcyan_skillfish_ppt.c57 uint32_t sclk; member
317 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n", in cyan_skillfish_print_clk_levels()
374 * cyan_skillfish specific, query default sclk inseted of hard code. in cyan_skillfish_is_dpm_running()
454 dev_err(smu->adev->dev, "Invalid sclk! Valid sclk range: %uMHz - %uMhz\n", in cyan_skillfish_od_edit_dpm_table()
466 cyan_skillfish_user_settings.sclk = input[1]; in cyan_skillfish_od_edit_dpm_table()
476 cyan_skillfish_user_settings.sclk = cyan_skillfish_sclk_default; in cyan_skillfish_od_edit_dpm_table()
486 if (cyan_skillfish_user_settings.sclk < CYAN_SKILLFISH_SCLK_MIN || in cyan_skillfish_od_edit_dpm_table()
487 cyan_skillfish_user_settings.sclk > CYAN_SKILLFISH_SCLK_MAX) { in cyan_skillfish_od_edit_dpm_table()
488 dev_err(smu->adev->dev, "Invalid sclk! Valid sclk range: %uMHz - %uMhz\n", in cyan_skillfish_od_edit_dpm_table()
502 cyan_skillfish_user_settings.sclk, NULL); in cyan_skillfish_od_edit_dpm_table()
[all …]
/linux/drivers/power/reset/
H A Dat91-poweroff.c55 struct clk *sclk; member
162 at91_shdwc.sclk = devm_clk_get(&pdev->dev, NULL); in at91_poweroff_probe()
163 if (IS_ERR(at91_shdwc.sclk)) in at91_poweroff_probe()
164 return PTR_ERR(at91_shdwc.sclk); in at91_poweroff_probe()
166 ret = clk_prepare_enable(at91_shdwc.sclk); in at91_poweroff_probe()
201 clk_disable_unprepare(at91_shdwc.sclk); in at91_poweroff_probe()
213 clk_disable_unprepare(at91_shdwc.sclk); in at91_poweroff_remove()
/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-g12.dtsi21 clock-names = "sclk", "lrclk", "mclk";
32 clock-names = "sclk", "lrclk", "mclk";
43 clock-names = "sclk", "lrclk", "mclk";
207 clock-names = "pclk", "sclk", "sclk_sel",
222 clock-names = "pclk", "sclk", "sclk_sel",
237 clock-names = "pclk", "sclk", "sclk_sel",
252 clock-names = "pclk", "sclk", "sclk_sel",
294 clock-names = "pclk", "sclk", "sclk_sel",
309 clock-names = "pclk", "sclk", "sclk_sel",
324 clock-names = "pclk", "sclk", "sclk_sel",
/linux/sound/soc/xilinx/
H A Dxlnx_i2s.c98 unsigned int bits_per_sample, sclk, sclk_div; in xlnx_i2s_hw_params() local
105 sclk = params_rate(params) * bits_per_sample * params_channels(params); in xlnx_i2s_hw_params()
106 sclk_div = drv_data->sysclk / sclk / 2; in xlnx_i2s_hw_params()
108 if ((drv_data->sysclk % sclk != 0) || in xlnx_i2s_hw_params()
110 dev_warn(i2s_dai->dev, "invalid SCLK divisor for sysclk %u and sclk %u\n", in xlnx_i2s_hw_params()
111 drv_data->sysclk, sclk); in xlnx_i2s_hw_params()
/linux/Documentation/devicetree/bindings/crypto/
H A Drockchip,rk3288-crypto.yaml55 - const: sclk
75 - const: sclk
94 - const: sclk
124 clock-names = "aclk", "hclk", "sclk", "apb_pclk";
/linux/Documentation/devicetree/bindings/rtc/
H A Dmoxa,moxart-rtc.txt6 - rtc-sclk-gpios : RTC sclk gpio, with zero flags
14 rtc-sclk-gpios = <&gpio 5 0>;

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