1*c66ec88fSEmmanuel VadotAnalog Devices AD2S90 Resolver-to-Digital Converter 2*c66ec88fSEmmanuel Vadot 3*c66ec88fSEmmanuel Vadothttps://www.analog.com/en/products/ad2s90.html 4*c66ec88fSEmmanuel Vadot 5*c66ec88fSEmmanuel VadotRequired properties: 6*c66ec88fSEmmanuel Vadot - compatible: should be "adi,ad2s90" 7*c66ec88fSEmmanuel Vadot - reg: SPI chip select number for the device 8*c66ec88fSEmmanuel Vadot - spi-max-frequency: set maximum clock frequency, must be 830000 9*c66ec88fSEmmanuel Vadot - spi-cpol and spi-cpha: 10*c66ec88fSEmmanuel Vadot Either SPI mode (0,0) or (1,1) must be used, so specify none or both of 11*c66ec88fSEmmanuel Vadot spi-cpha, spi-cpol. 12*c66ec88fSEmmanuel Vadot 13*c66ec88fSEmmanuel VadotSee for more details: 14*c66ec88fSEmmanuel Vadot Documentation/devicetree/bindings/spi/spi-bus.txt 15*c66ec88fSEmmanuel Vadot 16*c66ec88fSEmmanuel VadotNote about max frequency: 17*c66ec88fSEmmanuel Vadot Chip's max frequency, as specified in its datasheet, is 2Mhz. But a 600ns 18*c66ec88fSEmmanuel Vadot delay is expected between the application of a logic LO to CS and the 19*c66ec88fSEmmanuel Vadot application of SCLK, as also specified. And since the delay is not 20*c66ec88fSEmmanuel Vadot implemented in the spi code, to satisfy it, SCLK's period should be at most 21*c66ec88fSEmmanuel Vadot 2 * 600ns, so the max frequency should be 1 / (2 * 6e-7), which gives 22*c66ec88fSEmmanuel Vadot roughly 830000Hz. 23*c66ec88fSEmmanuel Vadot 24*c66ec88fSEmmanuel VadotExample: 25*c66ec88fSEmmanuel Vadotresolver@0 { 26*c66ec88fSEmmanuel Vadot compatible = "adi,ad2s90"; 27*c66ec88fSEmmanuel Vadot reg = <0>; 28*c66ec88fSEmmanuel Vadot spi-max-frequency = <830000>; 29*c66ec88fSEmmanuel Vadot spi-cpol; 30*c66ec88fSEmmanuel Vadot spi-cpha; 31*c66ec88fSEmmanuel Vadot}; 32