| /linux/sound/soc/ux500/ |
| H A D | ux500_msp_i2s.c | 138 writel(temp_reg, msp->registers + MSP_TCF); in set_prot_desc_tx()
166 writel(temp_reg, msp->registers + MSP_RCF); in set_prot_desc_rx()
203 temp_reg = readl(msp->registers + MSP_GCR) & ~TX_CLK_POL_RISING; in configure_protocol()
205 writel(temp_reg, msp->registers + MSP_GCR); in configure_protocol()
206 temp_reg = readl(msp->registers + MSP_GCR) & ~RX_CLK_POL_RISING; in configure_protocol()
208 writel(temp_reg, msp->registers + MSP_GCR); in configure_protocol()
222 reg_val_GCR = readl(msp->registers + MSP_GCR); in setup_bitclk()
223 writel(reg_val_GCR & ~SRG_ENABLE, msp->registers + MSP_GCR); in setup_bitclk()
255 writel(temp_reg, msp->registers + MSP_SRG); in setup_bitclk()
261 reg_val_GCR = readl(msp->registers + MSP_GCR); in setup_bitclk()
[all …]
|
| /linux/Documentation/trace/coresight/ |
| H A D | coresight-etm4x-reference.rst | 17 ETMv4 registers that they effect. Note the register names are given without
23 :Trace Registers: {CONFIGR + others}
27 other registers to enable the features requested.
40 :Trace Registers: All
50 :Trace Registers: PRGCTLR, All hardware regs.
63 :Trace Registers: None.
75 :Trace Registers: None.
89 :Trace Registers: None.
102 :Trace Registers: ACVR[idx, idx+1], VIIECTLR
125 :Trace Registers: ACVR[idx]
[all …]
|
| /linux/Documentation/driver-api/media/drivers/ccs/ |
| H A D | ccs-regs.asc | 18 # general status registers
51 # frame format description registers
91 # analog gain description registers
110 # data format description registers
122 # general set-up registers
170 # integration time registers
174 # analog gain registers
179 # digital gain registers
182 # hdr control registers
203 # clock set-up registers
[all …]
|
| /linux/drivers/net/can/ctucanfd/ |
| H A D | ctucanfd_kregs.h | 97 /* DEVICE_ID VERSION registers */
102 /* MODE SETTINGS registers */
123 /* STATUS registers */
135 /* COMMAND registers */
144 /* INT_STAT registers */
158 /* INT_ENA_SET registers */
161 /* INT_ENA_CLR registers */
164 /* INT_MASK_SET registers */
167 /* INT_MASK_CLR registers */
170 /* BTR registers */
[all …]
|
| /linux/drivers/video/fbdev/i810/ |
| H A D | i810_regs.h | 25 * All GC registers are memory-mapped. In addition, the VGA and extended VGA registers
32 /* Instruction and Interrupt Control Registers (01000h 02FFFh) */
60 /* Memory Control Registers (03000h 03FFFh) */
66 /* Span Cursor Registers (04000h 04FFFh) */
69 /* I/O Control Registers (05000h 05FFFh) */
75 /* Clock Control and Power Management Registers (06000h 06FFFh) */
86 /* Overlay Registers (30000h 03FFFFh) */
146 /* LCD/TV-Out and HW DVD Registers (60000h 6FFFFh) */
158 /* Display and Cursor Control Registers (70000h 7FFFFh) */
172 /* VGA Registers */
[all …]
|
| /linux/include/uapi/linux/ |
| H A D | elf.h | 390 #define NT_PPC_VMX 0x100 /* PowerPC Altivec/VMX registers */
391 #define NT_PPC_SPE 0x101 /* PowerPC SPE/EVR registers */
392 #define NT_PPC_VSX 0x102 /* PowerPC VSX registers */
396 #define NT_PPC_EBB 0x106 /* Event Based Branch Registers */
397 #define NT_PPC_PMU 0x107 /* Performance Monitor Registers */
398 #define NT_PPC_TM_CGPR 0x108 /* TM checkpointed GPR Registers */
399 #define NT_PPC_TM_CFPR 0x109 /* TM checkpointed FPR Registers */
400 #define NT_PPC_TM_CVMX 0x10a /* TM checkpointed VMX Registers */
401 #define NT_PPC_TM_CVSX 0x10b /* TM checkpointed VSX Registers */
402 #define NT_PPC_TM_SPR 0x10c /* TM Special Purpose Registers */
[all …]
|
| /linux/drivers/accel/habanalabs/include/gaudi2/arc/ |
| H A D | gaudi2_arc_common_packets.h | 99 * Extension registers
104 * Extension registers
111 * Extension registers
118 * Extension registers
125 * Extension registers
133 * Extension registers
141 * Extension registers
149 * Extension registers
157 * Extension registers
163 * Extension registers
[all …]
|
| /linux/drivers/scsi/smartpqi/ |
| H A D | smartpqi_sis.c | 110 status = readl(&ctrl_info->registers->sis_firmware_status); in sis_wait_for_ctrl_ready_with_timeout()
116 &ctrl_info->registers->sis_mailbox[7])); in sis_wait_for_ctrl_ready_with_timeout()
151 status = readl(&ctrl_info->registers->sis_firmware_status); in sis_is_firmware_running()
161 readl(&ctrl_info->registers->sis_mailbox[7])); in sis_is_firmware_running()
168 return readl(&ctrl_info->registers->sis_firmware_status) & in sis_is_kernel_up()
174 return readl(&ctrl_info->registers->sis_product_identifier); in sis_get_product_id()
185 struct pqi_ctrl_registers __iomem *registers; in sis_send_sync_cmd() local
191 registers = ctrl_info->registers; in sis_send_sync_cmd()
194 writel(cmd, ®isters->sis_mailbox[0]); in sis_send_sync_cmd()
201 writel(params->mailbox[i], ®isters->sis_mailbox[i]); in sis_send_sync_cmd()
[all …]
|
| /linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | nxp,s32g2-siul2-pinctrl.yaml | 21 IMCR registers need to be revealed for kernel to configure pinmux.
41 - description: MSCR registers group 0 in SIUL2_0
42 - description: MSCR registers group 1 in SIUL2_1
43 - description: MSCR registers group 2 in SIUL2_1
44 - description: IMCR registers group 0 in SIUL2_0
45 - description: IMCR registers group 1 in SIUL2_1
46 - description: IMCR registers group 2 in SIUL2_1
96 /* MSCR0-MSCR101 registers on siul2_0 */
98 /* MSCR112-MSCR122 registers on siul2_1 */
100 /* MSCR144-MSCR190 registers on siul2_1 */
[all …]
|
| /linux/sound/soc/codecs/ |
| H A D | tlv320aic3x.h | 57 /* ADC PGA Gain control registers */
60 /* MIC3 control registers */
63 /* Line1 Input control registers */
68 /* Line2 Input control registers */
74 /* AGC Control Registers A, B, C */
82 /* DAC Power and Left High Power Output control registers */
85 /* Right High Power Output control registers */
89 /* DAC Output Switching control registers */
91 /* High Power Output Driver Pop Reduction registers */
93 /* DAC Digital control registers */
[all …]
|
| /linux/Documentation/devicetree/bindings/dma/ti/ |
| H A D | k3-bcdma.yaml | 21 directly to memory mapped registers or area.
28 PDMAs can be configured via BCDMA split channel's peer registers to match with
145 - description: BCDMA Control /Status Registers region
146 - description: RX Channel Realtime Registers region
147 - description: Ring Realtime Registers region
168 - description: BCDMA Control /Status Registers region
169 - description: Block Copy Channel Realtime Registers region
170 - description: RX Channel Realtime Registers region
171 - description: TX Channel Realtime Registers region
172 - description: Ring Realtime Registers region
[all …]
|
| /linux/arch/xtensa/variants/csp/include/variant/ |
| H A D | tie-asm.h | 58 * (not including zero-overhead loop registers).
62 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
63 * registers are clobbered, the remaining are unused).
70 * select Select what category(ies) of registers to store, as a bitmask
71 * (see XTHAL_SAS_xxx constants). Defaults to all registers.
72 * alloc Select what category(ies) of registers to allocate; if any
74 * the corresponding registers is skipped without doing any store.
78 // Optional global registers used by default by the compiler:
88 // Optional caller-saved registers used by default by the compiler:
100 // Optional caller-saved registers not used by default by the compiler:
[all …]
|
| /linux/arch/xtensa/variants/de212/include/variant/ |
| H A D | tie-asm.h | 58 * (not including zero-overhead loop registers).
62 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
63 * registers are clobbered, the remaining are unused).
70 * select Select what category(ies) of registers to store, as a bitmask
71 * (see XTHAL_SAS_xxx constants). Defaults to all registers.
72 * alloc Select what category(ies) of registers to allocate; if any
74 * the corresponding registers is skipped without doing any store.
78 // Optional caller-saved registers used by default by the compiler:
90 // Optional caller-saved registers not used by default by the compiler:
112 * (not including zero-overhead loop registers).
[all …]
|
| /linux/drivers/net/ethernet/intel/ice/ |
| H A D | ice_ptp_hw.h | 114 * P_REG_DESK_PAR* registers may represent different clock markers at
136 * struct ice_eth56g_mac_reg_cfg - MAC config values for specific PTP registers
149 * All fixed point registers except Rx offset are 23 bit unsigned ints with
372 * change, such as an update to the CGU registers.
494 /* Timestamp memory reset registers */
499 /* Timestamp availability status registers */
503 /* Tx FIFO status registers */
511 /* Interrupt control Config registers */
519 /* Tx Timestamp data registers */
526 /* Timestamp init registers */
[all …]
|
| /linux/drivers/media/radio/si470x/ |
| H A D | radio-si470x-common.c | 185 radio->registers[SYSCONFIG2] &= ~SYSCONFIG2_BAND; in si470x_set_band()
186 radio->registers[SYSCONFIG2] |= radio->band << 6; in si470x_set_band()
203 if ((radio->registers[POWERCFG] & (POWERCFG_ENABLE|POWERCFG_DMUTE)) in si470x_set_chan()
209 radio->registers[CHANNEL] &= ~CHANNEL_CHAN; in si470x_set_chan()
210 radio->registers[CHANNEL] |= CHANNEL_TUNE | chan; in si470x_set_chan()
222 if ((radio->registers[STATUSRSSI] & STATUSRSSI_STC) == 0) in si470x_set_chan()
229 radio->registers[CHANNEL] &= ~CHANNEL_TUNE; in si470x_set_chan()
242 switch ((radio->registers[SYSCONFIG2] & SYSCONFIG2_SPACE) >> 4) { in si470x_get_step()
265 chan = radio->registers[READCHAN] & READCHAN_READCHAN; in si470x_get_freq()
327 radio->registers[POWERCFG] |= POWERCFG_SEEK; in si470x_set_seek()
[all …]
|
| /linux/arch/mips/include/uapi/asm/ |
| H A D | kvm.h | 49 * registers. The id field is broken down as follows:
55 * Register set = 0: GP registers from kvm_regs (see definitions below).
57 * Register set = 1: CP0 registers.
60 * COP0 register set = 0: Main CP0 registers.
67 * Register set = 2: KVM specific registers (see definitions below).
69 * Register set = 3: FPU / MSA registers (see definitions below).
71 * Other sets registers may be added in the future. Each set would
82 * KVM_REG_MIPS_GP - General purpose registers from kvm_regs.
124 * KVM_REG_MIPS_CP0 - Coprocessor 0 registers.
133 * KVM_REG_MIPS_KVM - KVM specific control registers.
[all …]
|
| /linux/Documentation/devicetree/bindings/display/msm/ |
| H A D | gmu.yaml | 100 - description: Core GMU registers
101 - description: GMU PDC registers
102 - description: GMU PDC sequence registers
132 - description: Core GMU registers
133 - description: Resource controller registers
134 - description: GMU PDC registers
169 - description: Core GMU registers
170 - description: GMU PDC registers
171 - description: GMU PDC sequence registers
188 - description: Core GMU registers
[all …]
|
| /linux/arch/xtensa/variants/dc233c/include/variant/ |
| H A D | tie-asm.h | 59 * (not including zero-overhead loop registers).
63 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
64 * registers are clobbered, the remaining are unused).
71 * select Select what category(ies) of registers to store, as a bitmask
72 * (see XTHAL_SAS_xxx constants). Defaults to all registers.
73 * alloc Select what category(ies) of registers to allocate; if any
75 * the corresponding registers is skipped without doing any store.
89 // Optional caller-saved registers used by default by the compiler:
101 // Optional caller-saved registers not used by default by the compiler:
123 * (not including zero-overhead loop registers).
[all …]
|
| /linux/tools/testing/selftests/powerpc/tm/ |
| H A D | tm-signal-context-chk-vsx.c | 16 * speculative nature of the 'live' registers and may infer the wrong
33 #define NV_VSX_REGS 12 /* Number of VSX registers to check. */
41 /* Test only 12 vsx registers from vsr20 to vsr31 */
66 * FP registers and VMX registers overlap the VSX registers. in signal_usr1()
68 * FP registers (f0-31) overlap the most significant 64 bits of VSX in signal_usr1()
69 * registers vsr0-31, whilst VMX registers vr0-31, being 128-bit like in signal_usr1()
70 * the VSX registers, overlap fully the other half of VSX registers, in signal_usr1()
74 * appeared first on the architecture), VMX registers vr0-31 (so VSX in signal_usr1()
81 * registers, but only the least significant 64 bits of vsr0-31. The in signal_usr1()
83 * registers, is kept in fp_regs. in signal_usr1()
[all …]
|
| /linux/arch/riscv/include/uapi/asm/ |
| H A D | kvm.h | 41 /* definition of registers in kvm_run */
49 /* CONFIG registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
60 /* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
70 /* General CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
85 /* AIA CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
101 /* TIMER registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
200 /* SBI STA extension registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
219 /* Config registers are mapped as type 1 */
224 /* Core registers are mapped as type 2 */
229 /* Control and status registers are mapped as type 3 */
[all …]
|
| /linux/arch/xtensa/variants/test_kc705_be/include/variant/ |
| H A D | tie-asm.h | 58 * (not including zero-overhead loop registers).
62 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
63 * registers are clobbered, the remaining are unused).
70 * select Select what category(ies) of registers to store, as a bitmask
71 * (see XTHAL_SAS_xxx constants). Defaults to all registers.
72 * alloc Select what category(ies) of registers to allocate; if any
74 * the corresponding registers is skipped without doing any store.
78 // Optional global registers used by default by the compiler:
88 // Optional caller-saved registers used by default by the compiler:
100 // Optional caller-saved registers not used by default by the compiler:
[all …]
|
| /linux/Documentation/devicetree/bindings/powerpc/nintendo/ |
| H A D | wii.txt | 31 - reg : should contain the VI registers location and length
42 - reg : should contain the PI registers location and length
64 - reg : should contain the DSP registers location and length
76 - reg : should contain the SI registers location and length
87 - reg : should contain the AI registers location and length
97 - reg : should contain the EXI registers location and length
107 - reg : should contain the EHCI registers location and length
117 - reg : should contain the SDHCI registers location and length
126 - reg : should contain the IPC registers location and length
138 - reg : should contain the controller registers location and length
[all …]
|
| /linux/tools/testing/selftests/kvm/ |
| H A D | get-reg-list.c | 9 * list new registers with get-reg-list. We assume they'll be unused, at
12 * registers which the source host with the older kernel has, then that's
15 * missing registers, but if new ones appear then they can probably be
204 * same value. Some registers may allow other values to be written in run_test()
206 * for ID registers set will fail if the value does not exactly match in run_test()
207 * what was returned by get. If registers that allow other values to in run_test()
212 * Only do the get/set tests on present, blessed list registers, in run_test()
213 * since we don't know the capabilities of any new registers. in run_test()
233 /* rejects_set registers are rejected for set operation */ in run_test()
246 /* skips_set registers are skipped for set operation */ in run_test()
[all …]
|
| /linux/tools/arch/mips/include/uapi/asm/ |
| H A D | kvm.h | 47 * registers. The id field is broken down as follows:
53 * Register set = 0: GP registers from kvm_regs (see definitions below).
55 * Register set = 1: CP0 registers.
60 * Register set = 2: KVM specific registers (see definitions below).
62 * Register set = 3: FPU / MSA registers (see definitions below).
64 * Other sets registers may be added in the future. Each set would
75 * KVM_REG_MIPS_GP - General purpose registers from kvm_regs.
117 * KVM_REG_MIPS_KVM - KVM specific control registers.
136 * disable). Any reads and writes of Count related registers while
152 * KVM_REG_MIPS_FPU - Floating Point and MIPS SIMD Architecture (MSA) registers.
[all …]
|
| /linux/Documentation/bpf/ |
| H A D | classic_vs_extended.rst | 12 - Number of registers increase from 2 to 10:
14 The old format had two registers A and X, and a hidden frame pointer. The
15 new layout extends this to be 10 internal registers and a read-only frame
16 pointer. Since 64-bit CPUs are passing arguments to functions via registers
19 function. Natively, x86_64 passes first 6 arguments in registers, aarch64/
20 sparcv9/mips64 have 7 - 8 registers for arguments; x86_64 has 6 callee saved
21 registers, and aarch64/sparcv9/mips64 have 11 or more callee saved registers.
23 Thus, all eBPF registers map one to one to HW registers on x86_64, aarch64,
30 R0 - R5 are scratch registers and eBPF program needs spill/fill them if
38 via 32-bit subregisters. All eBPF registers are 64-bit with 32-bit lower
[all …]
|