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/linux/drivers/net/phy/
H A Dlinkmode.c1 // SPDX-License-Identifier: GPL-2.0+
5 * linkmode_resolve_pause - resolve the allowable pause modes
21 * 1 X 1 X TX+RX
22 * 1 1 0 1 RX
47 * linkmode_set_pause - set the pause mode advertisement
50 * @rx: boolean from ethtool struct ethtool_pauseparam rx_pause member
53 * capabilities of provided in @tx and @rx.
56 * tx rx Pause AsymDir
62 * Note: this translation from ethtool tx/rx notation to the advertisement
65 * For tx=0 rx=1, meaning transmit is unsupported, receive is supported:
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/linux/Documentation/virt/kvm/
H A Dppc-pv.rst1 .. SPDX-License-Identifier: GPL-2.0
35 'hypercall-instructions'. This property contains at most 4 opcodes that make
43 r0 - volatile
53 r12 - volatile
80 applicable to the target. For now, we always map the page to -4096. This way we
84 ld rX, -4096(0)
89 registers. Only if the host supports the additional features, make use of them.
128 not require direct hypervisor intervention because they only get interpreted
133 - MSR_EE
134 - MSR_RI
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/linux/drivers/firmware/tegra/
H A Divc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
47 * This structure is divided into two-cache aligned parts, the first is only
48 * written through the tx.channel pointer, while the second is only written
49 * through the rx.channel pointer. This delineates ownership of the cache
50 * lines, which is critical to performance and necessary in non-cache coherent
68 } rx; member
79 if (!ivc->peer) in tegra_ivc_invalidate()
82 dma_sync_single_for_cpu(ivc->peer, phys, TEGRA_IVC_ALIGN, in tegra_ivc_invalidate()
88 if (!ivc->peer) in tegra_ivc_flush()
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/linux/drivers/net/wan/
H A Dhd64572.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * hd64572.h Description of the Hitachi HD64572 (SCA-II), valid for
8 * Copyright: (c) 2000-2001 Cyclades Corp.
15 * PC300 initial CVS version (3.4.0-pre1)
47 #define DRX_REG(reg, chan) (reg + 0x40*chan) /* DMA Rx */
49 #define TRX_REG(reg, chan) (reg + 0x20*chan) /* Timer Rx */
52 #define IR0_DRX(val, chan) ((val)<<(8*(chan))) /* Int DMA Rx */
65 #define RXS 0x13c /* RX clock source */
69 #define TMCR 0x145 /* Time constant (Rx) */
85 #define TRBL 0x100 /* TX/RX buffer reg L */
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/linux/drivers/net/wireless/ath/ath10k/
H A Drx_desc.h1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
56 * A-MPDU frame but a stand alone MPDU. Interior MPDU in an
57 * A-MPDU shall have both first_mpdu and last_mpdu bits set to
58 * 0. The PPDU start status will only be valid when this bit
63 * PPDU end status will only be valid when this bit is set.
66 * Multicast / broadcast indicator. Only set when the MAC
68 * matches one of the 4 BSSID registers. Only set when
73 * count. Only set when first_msdu is set.
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/linux/Documentation/devicetree/bindings/usb/
H A Dsnps,dwc3-common.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/snps,dwc3-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felipe Balbi <balbi@kernel.org>
14 vendor-specific implementation or as a standalone component.
17 - $ref: usb-drd.yaml#
18 - if:
24 - dr_mode
28 $ref: usb-xhci.yaml#
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/linux/Documentation/networking/
H A Daf_xdp.rst1 .. SPDX-License-Identifier: GPL-2.0
20 XDP programs to redirect frames to a memory buffer in a user-space
24 syscall. Associated with each XSK are two rings: the RX ring and the
25 TX ring. A socket can receive packets on the RX ring and it can send
28 to have at least one of these rings for each socket. An RX or TX
30 UMEM. RX and TX can share the same UMEM so that a packet does not have
31 to be copied between RX and TX. Moreover, if a packet needs to be kept
44 to fill in with RX packet data. References to these frames will then
45 appear in the RX ring once each packet has been received. The
48 space, for either TX or RX. Thus, the frame addrs appearing in the
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/linux/drivers/net/ethernet/google/gve/
H A Dgve_rx.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * Copyright (C) 2015-2021 Google, Inc.
19 dma_addr_t dma = (dma_addr_t)(be64_to_cpu(data_slot->addr) & in gve_rx_free_buffer()
22 page_ref_sub(page_info->page, page_info->pagecnt_bias - 1); in gve_rx_free_buffer()
23 gve_free_page(dev, page_info->page, dma, DMA_FROM_DEVICE); in gve_rx_free_buffer()
27 struct gve_rx_ring *rx, in gve_rx_unfill_pages() argument
30 u32 slots = rx->mask + 1; in gve_rx_unfill_pages()
33 if (!rx->data.page_info) in gve_rx_unfill_pages()
36 if (rx->data.raw_addressing) { in gve_rx_unfill_pages()
38 gve_rx_free_buffer(&priv->pdev->dev, &rx->data.page_info[i], in gve_rx_unfill_pages()
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/linux/drivers/net/ethernet/marvell/
H A Dskge.h1 /* SPDX-License-Identifier: GPL-2.0 */
133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
136 CS_VAUX_AVAIL = 1<<10,/* VAUX available (YUKON only) */
153 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
175 IS_EXT_REG = 1<<23, /* IRQ from LM80 or PHY (GENESIS only) */
176 /* IRQ from PHY (YUKON only) */
217 IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
218 IS_IRQ_SENSOR = 1<<12, /* IRQ from Sensor (YUKON only) */
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H A Dsky2.h1 /* SPDX-License-Identifier: GPL-2.0 */
30 /* Yukon-2 */
32 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
33 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
34 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
35 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
36 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
37 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
38 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
60 /* PCI_OUR_REG_3 32 bit Our Register 3 (Yukon-ECU only) */
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/linux/Documentation/networking/device_drivers/ethernet/freescale/
H A Ddpaa.rst1 .. SPDX-License-Identifier: GPL-2.0
8 - Madalin Bucur <madalin.bucur@nxp.com>
9 - Camelia Groza <camelia.groza@nxp.com>
13 - DPAA Ethernet Overview
14 - DPAA Ethernet Supported SoCs
15 - Configuring DPAA Ethernet in your kernel
16 - DPAA Ethernet Frame Processing
17 - DPAA Ethernet Features
18 - DPAA IRQ Affinity and Receive Side Scaling
19 - Debugging
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/linux/include/linux/mfd/
H A Dipaq-micro.h1 /* SPDX-License-Identifier: GPL-2.0 */
31 #define MSG_BACKLIGHT 0xd /* H3600 only */
32 #define MSG_CODEC_CTRL 0xe /* H3100 only */
33 #define MSG_DISPLAY_CTRL 0xf /* H3100 only */
44 * struct ipaq_micro_txdev - TX state
56 * struct ipaq_micro_rxdev - RX state
57 * @state: context of RX state machine
60 * @len: RX buffer length
61 * @index: RX buffer index
62 * @buf: RX buffer
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/linux/Documentation/networking/device_drivers/can/freescale/
H A Dflexcan.rst1 .. SPDX-License-Identifier: GPL-2.0+
7 Authors: Marc Kleine-Budde <mkl@pengutronix.de>,
13 For most flexcan IP cores the driver supports 2 RX modes:
15 - FIFO
16 - mailbox
19 and i.MX53 SOCs) only receive RTR frames if the controller is
20 configured for RX-FIFO mode.
22 The RX FIFO mode uses a hardware FIFO with a depth of 6 CAN frames,
30 With the "rx-rtr" private flag the ability to receive RTR frames can
34 "rx-rtr" on
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/linux/Documentation/devicetree/bindings/net/
H A Dkeystone-netcp.txt6 switch sub-module to send and receive packets. NetCP also includes a packet
13 includes a 3-port Ethernet switch sub-module capable of 10Gb/s and 1Gb/s rates
16 Keystone NetCP driver has a plug-in module architecture where each of the NetCP
17 sub-modules exist as a loadable kernel module which plug in to the netcp core.
18 These sub-modules are represented as "netcp-devices" in the dts bindings. It is
19 mandatory to have the ethernet switch sub-module for the ethernet interface to
20 be operational. Any other sub-module like the PA is optional.
24 -----------------------------
26 -----------------------------
28 |-> NetCP Devices -> |
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/linux/net/mac80211/
H A Drx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2002-2005, Instant802 Networks, Inc.
4 * Copyright 2005-2006, Devicescape Software, Inc.
5 * Copyright 2006-2007 Jiri Benc <jbenc@suse.cz>
6 * Copyright 2007-2010 Johannes Berg <johannes@sipsolutions.net>
7 * Copyright 2013-2014 Intel Mobile Communications GmbH
8 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH
9 * Copyright (C) 2018-2025 Intel Corporation
28 #include "driver-ops.h"
41 * only useful for monitoring.
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/linux/drivers/net/ethernet/sun/
H A Dcassini.h1 /* SPDX-License-Identifier: GPL-2.0+ */
29 /* cassini register map: 2M memory mapped in 32-bit memory space accessible as
30 * 32-bit words. there is no i/o port access. REG_ addresses are
31 * shared between cassini and cassini+. REG_PLUS_ addresses only
32 * appear in cassini+. REG_MINUS_ addresses only appear in cassini.
42 * if rx weight == 1 and tx weight == 0, rx == 2x tx transfer credit
62 /* top level interrupts [0-9] are auto-cleared to 0 when the status
63 * register is read. second level interrupts [13 - 18] are cleared at
64 * the source. tx completion register 3 is replicated in [19 - 31]
81 from RX FIFO to host mem.
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H A Dsungem.h1 /* SPDX-License-Identifier: GPL-2.0 */
26 #define GREG_SEBSTATE_RXWON 0x00000004 /* RX won internal arbitration */
31 #define GREG_CFG_RXDMALIM 0x000007c0 /* RX DMA grant limit */
34 #define GREG_CFG_ENBUG2FIX 0x00001000 /* Fix Rx hang after overflow */
39 * This auto-clearing does not occur when the alias at GREG_STAT2
40 * is read instead. The rest of the interrupt bits only clear when
48 #define GREG_STAT_RXDONE 0x00000010 /* One RX frame arrived */
49 #define GREG_STAT_RXNOBUF 0x00000020 /* No free RX buffers available */
50 #define GREG_STAT_RXTAGERR 0x00000040 /* RX tag framing is corrupt */
53 #define GREG_STAT_RXMAC 0x00008000 /* RX MAC signalled interrupt */
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/linux/drivers/net/ethernet/broadcom/
H A Db44.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 #define DEVCTRL_MPM 0x00000040 /* Magic Packet PME Enable (B0 only) */
17 #define B44_BIST_STAT 0x000CUL /* Built-In Self-Test Status */
34 #define ISTAT_LS 0x00000020 /* Link Change (B0 only) */
43 #define ISTAT_RX 0x00010000 /* RX Interrupt */
52 #define B44_ADDR_LO 0x0088UL /* ENET Address Lo (B0 only) */
53 #define B44_ADDR_HI 0x008CUL /* ENET Address Hi (B0 only) */
57 #define B44_RXBURST 0x00A4UL /* RX Max Burst Length */
94 #define B44_DMARX_CTRL 0x0210UL /* DMA RX Control */
98 #define B44_DMARX_ADDR 0x0214UL /* DMA RX Descriptor Ring Address */
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/linux/drivers/tty/serial/
H A Dsunzilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
57 #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
67 #define RxINT_DISAB 0 /* Rx Int Disable */
68 #define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */
69 #define INT_ALL_Rx 0x10 /* Int on all Rx Characters or error */
70 #define INT_ERR_Rx 0x18 /* Int on error only */
81 #define RxENAB 0x1 /* Rx Enable */
84 #define RxCRC_ENAB 0x8 /* Rx CRC Enable */
87 #define Rx5 0x0 /* Rx 5 Bits/Character */
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/linux/drivers/net/ethernet/intel/idpf/
H A Didpf_txrx.h1 /* SPDX-License-Identifier: GPL-2.0-only */
29 /* Number of descriptors in a queue should be a multiple of 32. RX queue
71 * given RX completion queue has descriptors. This includes _ALL_ buffer
73 * you have a total of 1024 buffers so your RX queue _must_ have at least that
74 * many descriptors. This macro divides a given number of RX descriptors by
76 * can have without overrunning the RX queue.
88 #define IDPF_RX_BUFQ_WORKING_SET(rxq) ((rxq)->desc_count - 1)
92 if (unlikely(++(ntc) == (rxq)->desc_count)) { \
100 if (unlikely(++(idx) == (q)->desc_count)) \
111 * only relevant in flow scheduling mode
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/linux/arch/arm/include/debug/
H A Dicedcc.S1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1994-1999 Russell King
15 .macro senduart, rd, rx argument
19 .macro busyuart, rd, rx argument
21 mrc p14, 0, \rx, c0, c1, 0
22 tst \rx, #0x20000000
26 .macro waituartcts, rd, rx argument
29 .macro waituarttxrdy, rd, rx argument
34 mrc p14, 0, \rx, c0, c1, 0
35 tst \rx, #0x20000000
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H A D8250.S1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1994-2013 Russell King
15 .macro store, rd, rx:vararg
17 str \rd, \rx
21 .macro load, rd, rx:vararg
22 ldr \rd, \rx
26 .macro store, rd, rx:vararg
27 strb \rd, \rx
30 .macro load, rd, rx:vararg
31 ldrb \rd, \rx
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/linux/drivers/net/can/spi/mcp251xfd/
H A Dmcp251xfd-ram.c1 // SPDX-License-Identifier: GPL-2.0
3 // mcp251xfd - Microchip MCP251xFD Family CAN controller driver
6 // Marc Kleine-Budde <kernel@pengutronix.de>
9 #include "mcp251xfd-ram.h"
17 max = min_t(u8, obj->max, obj->fifo_num * config->fifo_depth); in can_ram_clamp()
18 return clamp(val, obj->min, max); in can_ram_clamp()
26 u8 fifo_num = obj->fifo_num; in can_ram_rounddown_pow_of_two()
35 * coalescing or only half of FIFO (FIFO Half Full in can_ram_rounddown_pow_of_two()
38 ret = min_t(u8, coalesce * 2, config->fifo_depth); in can_ram_rounddown_pow_of_two()
39 val -= ret; in can_ram_rounddown_pow_of_two()
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/linux/include/uapi/linux/
H A Dtipc_config.h1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
5 * Copyright (c) 2003-2006, Ericsson AB
6 * Copyright (c) 2005-2007, 2010-2011, Wind River Systems
51 * back. (In the future multi-message replies may be supported.)
68 * Accepted by own node, or by remote node only if remote management enabled.
71 #define TIPC_CMD_NOOP 0x0000 /* tx none, rx none */
72 #define TIPC_CMD_GET_NODES 0x0001 /* tx net_addr, rx node_info(s) */
73 #define TIPC_CMD_GET_MEDIA_NAMES 0x0002 /* tx none, rx media_name(s) */
74 #define TIPC_CMD_GET_BEARER_NAMES 0x0003 /* tx none, rx bearer_name(s) */
75 #define TIPC_CMD_GET_LINKS 0x0004 /* tx net_addr, rx link_info(s) */
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/linux/Documentation/networking/device_drivers/ethernet/intel/
H A Dice.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 2018-2021 Intel Corporation.
13 - Overview
14 - Identifying Your Adapter
15 - Important Notes
16 - Additional Features & Configurations
17 - Performance Optimization
28 This driver supports XDP (Express Data Path) and AF_XDP zero-copy. Note that
43 -------------------------------------------
54 1) Make sure that your system's physical memory is in a high-performance
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