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/linux/drivers/net/phy/
H A Dlinkmode.c1 // SPDX-License-Identifier: GPL-2.0+
5 * linkmode_resolve_pause - resolve the allowable pause modes
21 * 1 X 1 X TX+RX
22 * 1 1 0 1 RX
47 * linkmode_set_pause - set the pause mode advertisement
50 * @rx: boolean from ethtool struct ethtool_pauseparam rx_pause member
53 * capabilities of provided in @tx and @rx.
56 * tx rx Pause AsymDir
62 * Note: this translation from ethtool tx/rx notation to the advertisement
65 * For tx=0 rx=1, meaning transmit is unsupported, receive is supported:
[all …]
/linux/Documentation/virt/kvm/
H A Dppc-pv.rst1 .. SPDX-License-Identifier: GPL-2.0
35 'hypercall-instructions'. This property contains at most 4 opcodes that make
43 r0 - volatile
53 r12 - volatile
80 applicable to the target. For now, we always map the page to -4096. This way we
84 ld rX, -4096(0)
89 registers. Only if the host supports the additional features, make use of them.
128 not require direct hypervisor intervention because they only get interpreted
133 - MSR_EE
134 - MSR_RI
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/linux/Documentation/devicetree/bindings/sound/
H A Drockchip,i2s-tdm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/rockchip,i2s-tdm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
18 - $ref: dai-common.yaml#
23 - rockchip,px30-i2s-tdm
24 - rockchip,rk1808-i2s-tdm
25 - rockchip,rk3308-i2s-tdm
26 - rockchip,rk3568-i2s-tdm
[all …]
/linux/drivers/firmware/tegra/
H A Divc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
47 * This structure is divided into two-cache aligned parts, the first is only
48 * written through the tx.channel pointer, while the second is only written
49 * through the rx.channel pointer. This delineates ownership of the cache
50 * lines, which is critical to performance and necessary in non-cache coherent
68 } rx; member
79 if (!ivc->peer) in tegra_ivc_invalidate()
82 dma_sync_single_for_cpu(ivc->peer, phys, TEGRA_IVC_ALIGN, in tegra_ivc_invalidate()
88 if (!ivc->peer) in tegra_ivc_flush()
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/linux/Documentation/networking/device_drivers/ethernet/mellanox/mlx5/
H A Dcounters.rst1 .. SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
13 - `Overview`_
14 - `Groups`_
15 - `Types`_
16 - `Descriptions`_
27 ----------------------------------------
29 ---------------------------------------- ---------------------------------------- |
32 | ------------------- --------------- | | ------------------- --------------- | |
34 | ------------------- --------------- | | ------------------- --------------- | |
36 | ------------------- | | ------------------- | |
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/linux/drivers/spi/
H A Dspi-loopback-test.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * linux/drivers/spi/spi-loopback-test.c
23 #include "spi-test.h"
25 /* flag to only simulate transfers */
37 /* the device is jumpered for loopback - enabling some rx_buf tests */
56 /* run tests only for a specific length */
57 static int run_only_iter_len = -1;
60 "only run tests for a length of this number in iterate_len list");
62 /* run only a specific test */
63 static int run_only_test = -1;
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H A Dspi-bcm2835.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
11 * spi-atmel.c, Copyright (C) 2006 Atmel Corporation
19 #include <linux/dma-mapping.h>
76 #define DRV_NAME "spi-bcm2835"
85 * struct bcm2835_spi - BCM2835 SPI controller
88 * @cs_gpio: chip-select GPIO descriptor
90 * @irq: interrupt, signals TX FIFO empty or RX FIFO ¾ full
99 * @rx_prologue: bytes received without DMA if first RX sglist entry's
102 * @debugfs_dir: the debugfs directory - neede to remove debugfs when
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/linux/drivers/net/wan/
H A Dhd64572.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * hd64572.h Description of the Hitachi HD64572 (SCA-II), valid for
8 * Copyright: (c) 2000-2001 Cyclades Corp.
15 * PC300 initial CVS version (3.4.0-pre1)
47 #define DRX_REG(reg, chan) (reg + 0x40*chan) /* DMA Rx */
49 #define TRX_REG(reg, chan) (reg + 0x20*chan) /* Timer Rx */
52 #define IR0_DRX(val, chan) ((val)<<(8*(chan))) /* Int DMA Rx */
65 #define RXS 0x13c /* RX clock source */
69 #define TMCR 0x145 /* Time constant (Rx) */
85 #define TRBL 0x100 /* TX/RX buffer reg L */
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/linux/drivers/net/wireless/ath/ath10k/
H A Drx_desc.h1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
56 * A-MPDU frame but a stand alone MPDU. Interior MPDU in an
57 * A-MPDU shall have both first_mpdu and last_mpdu bits set to
58 * 0. The PPDU start status will only be valid when this bit
63 * PPDU end status will only be valid when this bit is set.
66 * Multicast / broadcast indicator. Only set when the MAC
68 * matches one of the 4 BSSID registers. Only set when
73 * count. Only set when first_msdu is set.
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/linux/drivers/net/ethernet/google/gve/
H A Dgve_rx.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * Copyright (C) 2015-2021 Google, Inc.
19 dma_addr_t dma = (dma_addr_t)(be64_to_cpu(data_slot->addr) & in gve_rx_free_buffer()
22 page_ref_sub(page_info->page, page_info->pagecnt_bias - 1); in gve_rx_free_buffer()
23 gve_free_page(dev, page_info->page, dma, DMA_FROM_DEVICE); in gve_rx_free_buffer()
27 struct gve_rx_ring *rx, in gve_rx_unfill_pages() argument
30 u32 slots = rx->mask + 1; in gve_rx_unfill_pages()
33 if (!rx->data.page_info) in gve_rx_unfill_pages()
36 if (rx->data.raw_addressing) { in gve_rx_unfill_pages()
38 gve_rx_free_buffer(&priv->pdev->dev, &rx->data.page_info[i], in gve_rx_unfill_pages()
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/linux/drivers/net/ethernet/marvell/
H A Dskge.h1 /* SPDX-License-Identifier: GPL-2.0 */
133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
136 CS_VAUX_AVAIL = 1<<10,/* VAUX available (YUKON only) */
153 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
175 IS_EXT_REG = 1<<23, /* IRQ from LM80 or PHY (GENESIS only) */
176 /* IRQ from PHY (YUKON only) */
217 IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
218 IS_IRQ_SENSOR = 1<<12, /* IRQ from Sensor (YUKON only) */
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H A Dsky2.h1 /* SPDX-License-Identifier: GPL-2.0 */
30 /* Yukon-2 */
32 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
33 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
34 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
35 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
36 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
37 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
38 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
60 /* PCI_OUR_REG_3 32 bit Our Register 3 (Yukon-ECU only) */
[all …]
/linux/Documentation/networking/device_drivers/ethernet/freescale/
H A Ddpaa.rst1 .. SPDX-License-Identifier: GPL-2.0
8 - Madalin Bucur <madalin.bucur@nxp.com>
9 - Camelia Groza <camelia.groza@nxp.com>
13 - DPAA Ethernet Overview
14 - DPAA Ethernet Supported SoCs
15 - Configuring DPAA Ethernet in your kernel
16 - DPAA Ethernet Frame Processing
17 - DPAA Ethernet Features
18 - DPAA IRQ Affinity and Receive Side Scaling
19 - Debugging
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/linux/include/linux/mfd/
H A Dipaq-micro.h1 /* SPDX-License-Identifier: GPL-2.0 */
31 #define MSG_BACKLIGHT 0xd /* H3600 only */
32 #define MSG_CODEC_CTRL 0xe /* H3100 only */
33 #define MSG_DISPLAY_CTRL 0xf /* H3100 only */
44 * struct ipaq_micro_txdev - TX state
56 * struct ipaq_micro_rxdev - RX state
57 * @state: context of RX state machine
60 * @len: RX buffer length
61 * @index: RX buffer index
62 * @buf: RX buffer
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/linux/Documentation/networking/device_drivers/can/freescale/
H A Dflexcan.rst1 .. SPDX-License-Identifier: GPL-2.0+
7 Authors: Marc Kleine-Budde <mkl@pengutronix.de>,
13 For most flexcan IP cores the driver supports 2 RX modes:
15 - FIFO
16 - mailbox
19 and i.MX53 SOCs) only receive RTR frames if the controller is
20 configured for RX-FIFO mode.
22 The RX FIFO mode uses a hardware FIFO with a depth of 6 CAN frames,
30 With the "rx-rtr" private flag the ability to receive RTR frames can
34 "rx-rtr" on
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/linux/Documentation/networking/devlink/
H A Dmlx5.rst1 .. SPDX-License-Identifier: GPL-2.0
13 .. list-table:: Generic parameters implemented
15 * - Name
16 - Mode
17 - Validation
18 * - ``enable_roce``
19 - driverinit
20 - Type: Boolean
24 driver stack. When RoCE is disabled at the driver level, only raw
26 * - ``io_eq_size``
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/linux/Documentation/userspace-api/media/cec/
H A Dcec-pin-error-inj.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
8 The CEC Pin Framework is a core CEC framework for CEC hardware that only
9 has low-level support for the CEC bus. Most hardware today will have
10 high-level CEC support where the hardware deals with driving the CEC bus,
19 Currently only the cec-gpio driver (when the CEC line is directly
20 connected to a pull-up GPIO line) and the AllWinner A10/A20 drm driver
25 now an ``error-inj`` file.
32 With ``cat error-inj`` you can see both the possible commands and the current
35 $ cat /sys/kernel/debug/cec/cec0/error-inj
37 # clear clear all rx and tx error injections
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/linux/Documentation/devicetree/bindings/net/
H A Dkeystone-netcp.txt6 switch sub-module to send and receive packets. NetCP also includes a packet
13 includes a 3-port Ethernet switch sub-module capable of 10Gb/s and 1Gb/s rates
16 Keystone NetCP driver has a plug-in module architecture where each of the NetCP
17 sub-modules exist as a loadable kernel module which plug in to the netcp core.
18 These sub-modules are represented as "netcp-devices" in the dts bindings. It is
19 mandatory to have the ethernet switch sub-module for the ethernet interface to
20 be operational. Any other sub-module like the PA is optional.
24 -----------------------------
26 -----------------------------
28 |-> NetCP Devices -> |
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/linux/net/mac80211/
H A Drx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2002-2005, Instant802 Networks, Inc.
4 * Copyright 2005-2006, Devicescape Software, Inc.
5 * Copyright 2006-2007 Jiri Benc <jbenc@suse.cz>
6 * Copyright 2007-2010 Johannes Berg <johannes@sipsolutions.net>
7 * Copyright 2013-2014 Intel Mobile Communications GmbH
8 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH
9 * Copyright (C) 2018-2024 Intel Corporation
28 #include "driver-ops.h"
41 * only useful for monitoring.
[all …]
H A Dwpa.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2002-2004, Instant802 Networks, Inc.
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
6 * Copyright (C) 2020-2023 Intel Corporation
36 struct sk_buff *skb = tx->skb; in ieee80211_tx_h_michael_mic_add()
40 hdr = (struct ieee80211_hdr *)skb->data; in ieee80211_tx_h_michael_mic_add()
41 if (!tx->key || tx->key->conf.cipher != WLAN_CIPHER_SUITE_TKIP || in ieee80211_tx_h_michael_mic_add()
42 skb->len < 24 || !ieee80211_is_data_present(hdr->frame_control)) in ieee80211_tx_h_michael_mic_add()
45 hdrlen = ieee80211_hdrlen(hdr->frame_control); in ieee80211_tx_h_michael_mic_add()
46 if (skb->len < hdrlen) in ieee80211_tx_h_michael_mic_add()
[all …]
/linux/drivers/net/ethernet/sun/
H A Dcassini.h1 /* SPDX-License-Identifier: GPL-2.0+ */
29 /* cassini register map: 2M memory mapped in 32-bit memory space accessible as
30 * 32-bit words. there is no i/o port access. REG_ addresses are
31 * shared between cassini and cassini+. REG_PLUS_ addresses only
32 * appear in cassini+. REG_MINUS_ addresses only appear in cassini.
42 * if rx weight == 1 and tx weight == 0, rx == 2x tx transfer credit
62 /* top level interrupts [0-9] are auto-cleared to 0 when the status
63 * register is read. second level interrupts [13 - 18] are cleared at
64 * the source. tx completion register 3 is replicated in [19 - 31]
81 from RX FIFO to host mem.
[all …]
/linux/Documentation/devicetree/bindings/serial/
H A Dmvebu-uart.txt2 e.g., Armada-3700.
5 - compatible:
6 - "marvell,armada-3700-uart" for the standard variant of the UART
7 (32 bytes FIFO, no DMA, level interrupts, 8-bit access to the
9 - "marvell,armada-3700-uart-ext" for the extended variant of the
10 UART (128 bytes FIFO, DMA, front interrupts, 8-bit or 32-bit
12 - reg: offset and length of the register set for the device.
13 - clocks: UART reference clock used to derive the baudrate. If no clock
14 is provided (possible only with the "marvell,armada-3700-uart"
15 compatible string for backward compatibility), it will only work
[all …]
/linux/drivers/net/ethernet/broadcom/
H A Db44.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 #define DEVCTRL_MPM 0x00000040 /* Magic Packet PME Enable (B0 only) */
17 #define B44_BIST_STAT 0x000CUL /* Built-In Self-Test Status */
34 #define ISTAT_LS 0x00000020 /* Link Change (B0 only) */
43 #define ISTAT_RX 0x00010000 /* RX Interrupt */
52 #define B44_ADDR_LO 0x0088UL /* ENET Address Lo (B0 only) */
53 #define B44_ADDR_HI 0x008CUL /* ENET Address Hi (B0 only) */
57 #define B44_RXBURST 0x00A4UL /* RX Max Burst Length */
94 #define B44_DMARX_CTRL 0x0210UL /* DMA RX Control */
98 #define B44_DMARX_ADDR 0x0214UL /* DMA RX Descriptor Ring Address */
[all …]
/linux/drivers/tty/serial/
H A Dsunzilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
57 #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
67 #define RxINT_DISAB 0 /* Rx Int Disable */
68 #define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */
69 #define INT_ALL_Rx 0x10 /* Int on all Rx Characters or error */
70 #define INT_ERR_Rx 0x18 /* Int on error only */
81 #define RxENAB 0x1 /* Rx Enable */
84 #define RxCRC_ENAB 0x8 /* Rx CRC Enable */
87 #define Rx5 0x0 /* Rx 5 Bits/Character */
[all …]
/linux/include/uapi/linux/
H A Dethtool.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
26 * have the same layout for 32-bit and 64-bit userland.
38 * struct ethtool_cmd - DEPRECATED, link control and status
43 * interface supports autonegotiation or auto-detection.
44 * Read-only.
48 * auto-detection.
56 * @autoneg: Enable/disable autonegotiation and auto-detection;
60 * Read-only.
62 * obsoleted by &struct ethtool_coalesce. Read-only; deprecated.
63 * @maxrxpkt: Historically used to report RX IRQ coalescing; now
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