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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVProcessors.td62 def GENERIC_RV64 : RISCVProcessorModel<"generic-rv64",
68 // to change to the appropriate rv32/rv64 version.
77 def ROCKET_RV64 : RISCVProcessorModel<"rocket-rv64",
340 def SYNTACORE_SCR3_RV64 : RISCVProcessorModel<"syntacore-scr3-rv64",
H A DRISCVRegisterInfo.td68 let SubRegRanges = SubRegRangeByHwMode<[RV32, RV64],
72 let SubRegRanges = SubRegRangeByHwMode<[RV32, RV64],
124 def XLenVT : ValueTypeByHwMode<[RV32, RV64],
126 // Allow f64 in GPR for ZDINX on RV64.
127 def XLenFVT : ValueTypeByHwMode<[RV64],
132 [RV32, RV64],
595 let RegInfos = RegInfoByHwMode<[RV32, RV64],
H A DRISCVTargetTransformInfo.h270 // Scalarize masked gather for RV64 if EEW=64 indices aren't supported. in forceScalarizeMaskedGather()
275 // Scalarize masked scatter for RV64 if EEW=64 indices aren't supported. in forceScalarizeMaskedScatter()
H A DRISCVSubtarget.cpp73 CPU = Is64Bit ? "generic-rv64" : "generic-rv32"; in initializeSubtargetDependencies()
H A DRISCVISelLowering.h107 // FP to XLen int conversions. Corresponds to fcvt.l(u).s/d/h on RV64 and
113 // FP to 32 bit int conversions for RV64. These are used to keep track of the
415 // FP to 32 bit int conversions for RV64. These are used to keep track of the
H A DRISCVInstrInfoM.td119 // Experimental RV64 i32 legalization patterns.
H A DRISCVInstrInfoXTHead.td626 // mulaw, mulsw are available only in RV64.
850 // Experimental RV64 i32 legalization patterns.
890 // mulaw, mulsw are available only in RV64.
H A DRISCVTargetMachine.cpp142 assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported"); in computeDataLayout()
H A DRISCVFeatures.td1282 : SubtargetFeature<"64bit", "IsRV64", "true", "Implements RV64">;
1291 def RV64 : HwMode<"+64bit", [IsRV64]>;
/freebsd/sys/contrib/device-tree/Bindings/riscv/
H A Dextensions.yaml241 RV64 as it contains no instructions") of riscv-code-size-reduction,
249 RV64 as it contains no instructions") of riscv-code-size-reduction,
257 RV64 as it contains no instructions") of riscv-code-size-reduction,
265 RV64 as it contains no instructions") of riscv-code-size-reduction,
610 # Zcf extension does not exist on rv64
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVBaseInfo.cpp113 report_fatal_error("RV64 target requires an RV64 CPU"); in validate()
118 report_fatal_error("RV32 and RV64 can't be combined"); in validate()
H A DRISCVMatInt.cpp81 assert(IsRV64 && "Can't emit >32-bit imm for non-RV64 target"); in generateInstSeqImpl()
254 // will always be true for RV32 and will often be true for RV64. in generateInstSeq()
H A DRISCVMCTargetDesc.cpp92 CPU = TT.isArch64Bit() ? "generic-rv64" : "generic-rv32"; in createRISCVMCSubtargetInfo()
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/
H A DEmulateInstructionRISCV.cpp510 {"C_LDSP", 0xE003, 0x6002, DecodeC_LDSP, RV64 | RV128},
512 {"C_SDSP", 0xE003, 0xE002, DecodeC_SDSP, RV64 | RV128},
514 {"C_LD", 0xE003, 0x6000, DecodeC_LD, RV64 | RV128},
516 {"C_SD", 0xE003, 0xE000, DecodeC_SD, RV64 | RV128},
525 {"C_ADDIW", 0xE003, 0x2001, DecodeC_ADDIW, RV64 | RV128},
527 {"C_SLLI", 0xE003, 0x2, DecodeC_SLLI, RV64 | RV128},
528 {"C_SRLI", 0xEC03, 0x8001, DecodeC_SRLI, RV64 | RV128},
529 {"C_SRAI", 0xEC03, 0x8401, DecodeC_SRAI, RV64 | RV128},
537 {"C_SUBW", 0xFC63, 0x9C01, DecodeC_SUBW, RV64 | RV128},
538 {"C_ADDW", 0xFC63, 0x9C21, DecodeC_ADDW, RV64 | RV128},
[all …]
H A DRISCVInstructions.h294 constexpr uint8_t RV64 = 2; variable
305 uint8_t inst_type = RV32 | RV64 | RV128;
/freebsd/contrib/llvm-project/clang/lib/Driver/ToolChains/Arch/
H A DRISCV.cpp248 // rv64g | rv64*d -> lp64d in getRISCVABI()
250 // rv64* -> lp64 in getRISCVABI()
395 return Triple.isRISCV64() ? "generic-rv64" : "generic-rv32"; in getRISCVTargetCPU()
/freebsd/contrib/llvm-project/compiler-rt/lib/builtins/riscv/
H A Dsave.S13 // The entry points are grouped up into 2s for rv64 and 4s for rv32 since this
H A Drestore.S17 // The entry points are grouped up into 2s for rv64 and 4s for rv32 since this
/freebsd/contrib/llvm-project/llvm/lib/TargetParser/
H A DRISCVISAInfo.cpp491 else if (Arch.consume_front("rv64")) in parseNormalizedArchString()
564 // ISA string must begin with rv32, rv64, or a profile. in parseArchString()
568 } else if (Arch.consume_front("rv64")) { in parseArchString()
604 "string must begin with rv32{i,e,g}, rv64{i,e,g}, or a supported " in parseArchString()
H A DRISCVTargetParser.cpp36 bool is64Bit() const { return DefaultMarch.starts_with("rv64"); } in is64Bit()
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A Driscv_sifive_vector.td53 ["Xsfvcp", "RV64"], ["Xsfvcp"]) in
H A Driscv_vector.td132 RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin", "RV64"],
133 !if(!eq(type, "y"), ["Zvfbfmin", "RV64"],
134 ["RV64"])) in {
239 RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin", "RV64"],
240 !if(!eq(type, "y"), ["Zvfbfmin", "RV64"],
241 ["RV64"])) in {
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp1003 /// True if this operand is for an RV64 instruction
2333 // If this is not an RV64 GPRPair instruction, don't parse as a GPRPair on in parseGPRPair()
2334 // RV64 as it will prevent matching the RV64 version of the same instruction in parseGPRPair()
2336 // If this is an RV64 GPRPair instruction, there is no RV32 version so we can in parseGPRPair()
2806 return Error(Loc, "bad arch string switching from rv64 to rv32"); in resetToArch()
2808 return Error(Loc, "bad arch string switching from rv32 to rv64"); in resetToArch()
/freebsd/sys/riscv/riscv/
H A Didentcpu.c135 * RISC-V CPU. The string begins with a small prefix (e.g. rv64) indicating the
/freebsd/sys/contrib/openzfs/config/
H A Dhost-cpu-c-abi.m4241 # There are 2 architectures (with variants): rv32* and rv64*.

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