| /linux/drivers/edac/ |
| H A D | i5000_edac.c | 12 * Intel 5000X Chipset Memory Controller Hub (MCH) - Datasheet
102 /* Non-Retry or redundant Retry errors */
276 /* Defines to extract the various fields from the
277 * MTRx - Memory Technology Registers
290 /* enables the report of miscellaneous messages as CE errors - default off */
363 u32 ferr_nf_fbd; /* First Errors Non-Fatal */
364 u32 nerr_nf_fbd; /* Next Errors Non-Fatal */
372 * Non-Recoverable Error */
373 u16 nrecmema; /* Non-Recoverable Mem log A */
374 u32 nrecmemb; /* Non-Recoverable Mem log B */
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| H A D | i5100_edac.c | 9 * Intel 5100X Chipset Memory Controller Hub (MCH) - Datasheet
13 * can not reflect this configuration so instead the chip-select
15 * the first half belonging to channel 0, the second half belonging
16 * to channel 1.
18 * This driver is for DDR2 DIMMs, and it uses chip select to select among the
70 #define I5100_NERR_NF_MEM 0xa4 /* MC Next Non-Fatal Errors */
82 #define I5100_MTR_0 0x154 /* Memory Technology Registers 0-3 */
85 #define I5100_NRECMEMA 0x190 /* Non-Recoverable Memory Error Log Reg A */
86 #define I5100_NRECMEMB 0x194 /* Non-Recoverable Memory Error Log Reg B */
127 return a & ((1 << 8) - 1); in i5100_spddata_data()
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| H A D | i5400_edac.c | 18 * Intel 5400 Chipset Memory Controller Hub (MCH) - Datasheet
21 * This Memory Controller manages DDR2 FB-DIMMs. It has 2 branches, each with
22 * 2 channels operating in lockstep no-mirror mode. Each channel can have up to
23 * 4 dimm's, each with up to 8GB.
83 #define FERR_FAT_FBDCHAN (3<<28) /* channel index where the highest-order error occurred */
88 /* Non-fatal error register */
140 * Error masks are according with Table 5-17 of i5400 datasheet
144 EMASK_M1 = 1<<0, /* Memory Write error on non-redundant retry */
145 EMASK_M2 = 1<<1, /* Memory or FB-DIMM configuration CRC read error */
148 EMASK_M5 = 1<<4, /* Aliased Uncorrectable Non-Mirrored Demand Data ECC */
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| H A D | i7300_edac.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 * Intel 7300 Chipset Memory Controller Hub (MCH) - Datasheet
16 * This driver uses "csrows" EDAC attribute to represent DIMM slot#
48 * Branch 0 - 2 channels: channels 0 and 1 (FDB0 PCI dev 21.0)
49 * Branch 1 - 2 channels: channels 2 and 3 (FDB1 PCI dev 22.0)
50 * Each channel can have to 8 DIMM sets (called as SLOTS)
115 /* FIXME: Why do we need to have this static? */
150 * Note: Other Intel EDAC drivers use AMBPRESENT to identify if the available
151 * memory. From datasheet item 7.3.1 (FB-DIMM technology & organization), it
153 * Each memory slot may have up to 2 AMB interfaces, one for income and another
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| H A D | r82600_edac.c | 12 * Written with reference to 82600 High Integration Dual PCI System
14 * www.radisys.com/files/support_downloads/007-01277-0002.82600DataBook.pdf
15 * references to this document given in []
34 * supports up to four banks of memory. The four banks can support a mix of
36 * each of which can be any size from 16MB to 512MB. Both registered (control
38 * registered and unbuffered DIMMs as well as mixing of ECC and non-ECC DIMMs
49 /* Radisys 82600 register addresses - device 0 function 0 - PCI bridge */
74 * 1=Drive ECC bits to 0 during
81 * 2 CAS# Latency 0=3clks 1=2clks
83 * 1 RAS# to CAS# Delay 0=3 1=2
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| H A D | i82975x_edac.c | 34 /* Intel 82975X register addresses - device 0 function 0 - DRAM Controller */
37 * 31:7 128 byte cache-line address
50 * More - See Page 65 of Intel DocSheet.
58 * 9 non-DRAM lock error (ndlock)
76 * 9 non-DRAM lock error (ndlock)
105 * 31:14 Base Addr of 16K memory-mapped
108 * 0 mem-mapped config space enable
111 /* NOTE: Following addresses have to indexed using MCHBAR offset (44h, 32b) */
118 * 7 set to 1 in highest DRB of
122 * 1:0 set to 0
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| /linux/arch/arm/mach-imx/ |
| H A D | pm-imx6.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2011-2014 Freescale Semiconductor, Inc.
13 #include <linux/irqchip/arm-gic.h>
15 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
24 #include <asm/proc-fns.h>
101 0x56c, 0x578, 0x588, 0x594, /* CAS, RAS, SDCLK_0, SDCLK_1 */
113 0x464, 0x490, 0x4ac, 0x4b0, /* CAS, RAS, SDCLK_0, SDCLK_1 */
125 0x300, 0x31c, 0x338, 0x5ac, /* CAS, RAS, SDCLK_0, GPR_ADDS */
140 0x300, 0x2fc, 0x32c, 0x5f4, /* CAS, RAS, SDCLK_0, GPR_ADDS */
146 0x244, 0x248, 0x24c, 0x250, /* DQM0, DQM1, RAS, CAS */
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| H A D | pm-imx5.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
45 * The WAIT_UNCLOCKED_POWER_OFF state only requires <= 500ns to exit.
47 * non-cpu parts of the system. For these reasons, imx5 should default
48 * to always using this state for cpu idling. The PM_SUSPEND_STANDBY also
49 * uses this state and needs to take no action when registers remain configured
79 {.offset = 0x574, .clear = MX53_DSE_HIGHZ_MASK}, /* CAS */
80 {.offset = 0x588, .clear = MX53_DSE_HIGHZ_MASK}, /* RAS */
96 /* Controls the CKE signal which is required to leave self refresh */
122 * suspend code(arch/arm/mach-imx/suspend-imx53.S), if this struct
124 * must be also changed accordingly otherwise, the suspend to ocram
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| /linux/arch/sparc/kernel/ |
| H A D | pci_sabre.c | 1 // SPDX-License-Identifier: GPL-2.0
55 #define SABRE_UECE_AFAR_ALIAS 0x0048UL /* Aliases to 0x0038 */
115 #define SABRE_PCICTRL_ARBPARK 0x0000000000200000UL /* Bus Parking 0=Ultra-IIi 1=prev-bus-owner */
116 #define SABRE_PCICTRL_CPUPRIO 0x0000000000100000UL /* Ultra-IIi granted every other bus cycle */
119 #define SABRE_PCICTRL_RTRYWE 0x0000000000000080UL /* DMA Flow Control 0=wait-if-possible 1=retry …
138 #define SABRE_PCIDIAG_ELPBK 0x0000000000000001UL /* Loopback Enable - not supported */
140 #define SABRE_PCITASR_EF 0x0000000000000080UL /* Respond to 0xe0000000-0xffffffff */
141 #define SABRE_PCITASR_CD 0x0000000000000040UL /* Respond to 0xc0000000-0xdfffffff */
142 #define SABRE_PCITASR_AB 0x0000000000000020UL /* Respond to 0xa0000000-0xbfffffff */
143 #define SABRE_PCITASR_89 0x0000000000000010UL /* Respond to 0x80000000-0x9fffffff */
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| /linux/Documentation/devicetree/bindings/memory-controllers/ddr/ |
| H A D | jedec,lpddr2-timings.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2-timings.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR2 SDRAM AC timing parameters for a given speed-bin
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 const: jedec,lpddr2-timings
16 max-freq:
19 Maximum DDR clock frequency for the speed-bin, in Hz.
21 min-freq:
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| H A D | jedec,lpddr3-timings.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3-timings.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR3 SDRAM AC timing parameters for a given speed-bin
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 const: jedec,lpddr3-timings
19 Maximum DDR clock frequency for the speed-bin, in Hz.
20 Property is deprecated, use max-freq.
23 max-freq:
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| H A D | jedec,lpddr2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR2 SDRAM compliant to JEDEC JESD209-2
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 - $ref: jedec,lpddr-props.yaml#
18 - items:
19 - enum:
20 - elpida,ECB240ABACN
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| H A D | jedec,lpddr3.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR3 SDRAM compliant to JEDEC JESD209-3
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 - $ref: jedec,lpddr-props.yaml#
18 - items:
19 - enum:
20 - samsung,K3QF2F20DB
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| /linux/arch/arm/mach-sa1100/include/mach/ |
| H A D | SA-1100.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * FILE SA-1100.h
9 * System StrongARM SA-1100
11 * Purpose Definition of constants related to the StrongARM
12 * SA-1100 microprocessor (Advanced RISC Machine (ARM)
14 * StrongARM SA-1100 data sheet version 2.2.
21 #error You must include hardware.h not SA-1100.h
27 * SA1100 CS line to physical address
91 * Controller (UDC) Control/Status register end-point 0
94 * Controller (UDC) Control/Status register end-point 1
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| /linux/arch/sh/boards/ |
| H A D | board-magicpanelr2.c | 1 // SPDX-License-Identifier: GPL-2.0
65 /* CS2: LAN (0x08000000 - 0x0bffffff) */ in setup_chip_select()
71 /* CS4: CAN1 (0xb0000000 - 0xb3ffffff) */ in setup_chip_select()
77 /* CS5a: CAN2 (0xb4000000 - 0xb5ffffff) */ in setup_chip_select()
83 /* CS5b: CAN3 (0xb6000000 - 0xb7ffffff) */ in setup_chip_select()
89 /* CS6a: Rotary (0xb8000000 - 0xb9ffffff) */ in setup_chip_select()
133 /* H7 (x); H6 /RAS(BRAS); H5 /CAS(BCAS); H4 CKE(BCKE); in setup_port_multiplexing()
270 .id = -1,
292 .id = -1,
301 /* Reserved for bootloader, read-only */
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| /linux/drivers/pinctrl/ |
| H A D | pinctrl-gemini.c | 6 * This is a group-only pin controller.
19 #include <linux/pinctrl/pinconf-generic.h>
24 #include "pinctrl-utils.h"
26 #define DRIVER_NAME "pinctrl-gemini"
29 * struct gemini_pin_conf - information about configuring a pin
41 * struct gemini_pmx - state holder for the gemini pin controller
42 * @dev: a pointer back to containing device
43 * @virtbase: the offset to the controller in virtual memory
44 * @map: regmap to access registers
64 * struct gemini_pin_group - describes a Gemini pin group
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| /linux/drivers/pinctrl/renesas/ |
| H A D | pfc-sh7264.c | 1 // SPDX-License-Identifier: GPL-2.0
52 /* NOTE - Port H does not have a Data Register, but PH Data is
53 connected to PH Port Register */
56 /* Port I - not on device */
105 /* Port H - Port H does not have a Data Register */
106 /* Port I - not on device */
155 /* Port H - Port H does not have a Data Register */
156 /* Port I - not on device */
403 /* Port I - not on device */
482 /* Port I - not on device */
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| H A D | pfc-sh7269.c | 1 // SPDX-License-Identifier: GPL-2.0
55 /* NOTE - Port H does not have a Data Register, but PH Data is
56 connected to PH Port Register */
59 /* Port I - not on device */
109 /* Port H - Port H does not have a Data Register */
110 /* Port I - not on device */
160 /* Port H - Port H does not have a Data Register */
161 /* Port I - not on device */
501 /* Port I - not on device */
1245 /* Port I - not on device */
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