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/linux/Documentation/devicetree/bindings/net/wireless/
H A Dqcom,ath10k.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff Johnson <jjohnson@kernel.org>
18 - qcom,ath10k # SDIO-based devices
19 - qcom,ipq4019-wifi
20 - qcom,wcn3990-wifi # SNoC-based devices
25 reg-names:
27 - const: membase
33 interrupt-names:
[all …]
/linux/Documentation/devicetree/bindings/thermal/
H A Dqcom-spmi-adc-tm-hc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/thermal/qcom-spmi-adc-tm-hc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
9 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
11 $ref: thermal-sensor.yaml#
15 const: qcom,spmi-adc-tm-hc
23 "#thermal-sensor-cells":
26 "#address-cells":
29 "#size-cells":
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H A Dqcom-spmi-adc-tm5.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/thermal/qcom-spmi-adc-tm5.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
9 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
11 $ref: thermal-sensor.yaml#
16 - qcom,spmi-adc-tm5
17 - qcom,spmi-adc-tm5-gen2
18 - qcom,adc-tm7 # Incomplete / subject to change
26 "#thermal-sensor-cells":
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/linux/arch/arm/boot/dts/qcom/
H A Dqcom-ipq4018-ap120c-ac.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 #include "qcom-ipq4019.dtsi"
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
8 model = "ALFA Network AP120C-AC";
9 compatible = "alfa-network,ap120c-ac", "qcom,ipq4018";
16 stdout-path = "serial0:115200n8";
20 compatible = "gpio-keys";
22 key-reset {
31 i2c0_pins: i2c0-state {
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/linux/Documentation/devicetree/bindings/input/
H A Dti,drv260x.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments - drv260x Haptics driver family
10 - Andrew Davis <afd@ti.com>
15 - ti,drv2604
16 - ti,drv2605
17 - ti,drv2605l
22 vbat-supply:
30 (defined in include/dt-bindings/input/ti-drv260x.h)
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/linux/drivers/net/wireless/ath/ath10k/
H A Dcore.c1 // SPDX-License-Identifier: ISC
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
5 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
6 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
18 #include <linux/nvmem-consumer.h>
30 #include "wmi-ops.h"
59 MODULE_PARM_DESC(skip_otp, "Skip otp failure for calibration in testmode");
60 MODULE_PARM_DESC(cryptmode, "Crypto mode: 0-hardware, 1-software");
476 * or 2x2 160Mhz, long-guard-interval.
[all …]
/linux/drivers/phy/
H A Dphy-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
23 * | | | | ---------
24 * External Clock ------| | -------------
25 * |------|
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/linux/drivers/media/tuners/
H A Dfc0011.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * Copyright (C) 2012 Hans-Frieder Vogt <hfvogt@gmx.net>
51 FC11_VCOCAL_RUN = 0, /* VCO calibration run */
52 FC11_VCOCAL_VALUEMASK = 0x3F, /* VCO calibration value mask */
53 FC11_VCOCAL_OK = 0x40, /* VCO calibration Ok */
54 FC11_VCOCAL_RESET = 0x80, /* VCO calibration reset */
70 struct i2c_msg msg = { .addr = priv->addr, in fc0011_writereg()
73 if (i2c_transfer(priv->i2c, &msg, 1) != 1) { in fc0011_writereg()
74 dev_err(&priv->i2c->dev, in fc0011_writereg()
77 return -EIO; in fc0011_writereg()
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/linux/drivers/phy/xilinx/
H A Dphy-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
27 #include <dt-bindings/phy/phy.h>
33 /* TX De-emphasis parameters */
38 /* DN Resistor calibration code parameters */
87 /* Calibration digital logic parameters */
184 * struct xpsgtr_ssc - structure to hold SSC settings for a lane
198 * struct xpsgtr_phy - representation of a lane
219 * struct xpsgtr_dev - representation of a ZynMP GT device
[all …]
/linux/drivers/net/wireless/ath/ath9k/
H A Dlink.c20 * TX polling - checks if the TX engine is stuck somewhere
28 if (sc->tx99_state) in ath_tx_complete_check()
32 txq = sc->tx.txq_map[i]; in ath_tx_complete_check()
35 if (txq->axq_depth) { in ath_tx_complete_check()
36 if (txq->axq_tx_inprogress) { in ath_tx_complete_check()
41 txq->axq_tx_inprogress = true; in ath_tx_complete_check()
49 ath_dbg(ath9k_hw_common(sc->sc_ah), RESET, in ath_tx_complete_check()
59 struct ath_common *common = ath9k_hw_common(sc->sc_ah); in ath_hw_rx_inactive_check()
62 interval = jiffies_to_msecs(jiffies - sc->rx_active_check_time); in ath_hw_rx_inactive_check()
63 count = sc->rx_active_count; in ath_hw_rx_inactive_check()
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/linux/arch/arm/mach-omap2/
H A Dsdrc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
8 * Copyright (C) 2007-2008, 2012 Texas Instruments, Inc.
9 * Copyright (C) 2007-2008 Nokia Corporation
55 * struct omap_sdrc_params - SDRC parameters for a given SDRC clock rate
62 * This structure holds a pre-computed set of register values for the
64 * intended to be pre-computed and specified in an array in the board-*.c
112 /* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */
124 /* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
166 * become sub-optimal. The RFR value goes in the opposite direction. If you
170 * unlocked and their value needs run time calibration. A dynamic call is
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/linux/drivers/gpu/host1x/
H A Dmipi.c109 /* calibration settings for data lanes */
114 /* calibration settings for clock lanes */
139 return readl(mipi->regs + (offset << 2)); in tegra_mipi_readl()
145 writel(value, mipi->regs + (offset << 2)); in tegra_mipi_writel()
153 err = clk_enable(mipi->clk); in tegra_mipi_power_up()
160 if (mipi->soc->needs_vclamp_ref) in tegra_mipi_power_up()
169 clk_disable(mipi->clk); in tegra_mipi_power_up()
179 err = clk_enable(mipi->clk); in tegra_mipi_power_down()
194 * control a regulator that supplies current to the pre-driver logic. in tegra_mipi_power_down()
200 if (mipi->soc->needs_vclamp_ref) in tegra_mipi_power_down()
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/linux/drivers/input/keyboard/
H A Dqt1050.c1 // SPDX-License-Identifier: GPL-2.0
90 /* Calibration and Reset */
229 err = regmap_read(ts->regmap, QT1050_CHIP_ID, &val); in qt1050_identify()
231 dev_err(&ts->client->dev, "Failed to read chip ID: %d\n", err); in qt1050_identify()
236 dev_err(&ts->client->dev, "ID %d not supported\n", val); in qt1050_identify()
241 err = regmap_read(ts->regmap, QT1050_FW_VERSION, &val); in qt1050_identify()
243 dev_err(&ts->client->dev, "could not read the firmware version\n"); in qt1050_identify()
247 dev_info(&ts->client->dev, "AT42QT1050 firmware version %1d.%1d\n", in qt1050_identify()
256 struct input_dev *input = ts->input; in qt1050_irq_threaded()
262 err = regmap_read(ts->regmap, QT1050_DET_STATUS, &val); in qt1050_irq_threaded()
[all …]
/linux/Documentation/input/
H A Dgameport-programming.rst34 Please also consider enabling the gameport on the card in the ->open()
35 callback if the io is mapped to ISA space - this way it'll occupy the io
37 ->close() callback. You also can select the io address in the ->open()
70 the driver doesn't have to measure them the old way - an ADC is built into
86 return -(mode != GAMEPORT_MODE_COOKED);
97 See analog.c and input.c for handling of fuzz - the fuzz value determines
105 examples 1+2 or 1+3. Gameports can support internal calibration - see below,
107 more than one gameport instance simultaneously, use the ->private member of
147 I/O address for use with raw mode. You have to either set this, or ->read()
191 pre-filled by cooked data by the caller, max[0..3] should be pre-filled with
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dmediatek,tphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek T-PHY Controller
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 The T-PHY controller supports physical layer functionality for a number of
17 Layout differences of banks between T-PHY V1 (mt8173/mt2701) and
18 T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode:
19 -----------------------------------
62 added on V2; the FMREG bank for slew rate calibration is not used anymore
[all …]
/linux/drivers/scsi/
H A Dsense_codes.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * http://www.t10.org/lists/asc-num.txt [most recent: 20200817]
9 SENSE_CODE(0x0002, "End-of-partition/medium detected")
11 SENSE_CODE(0x0004, "Beginning-of-partition/medium detected")
12 SENSE_CODE(0x0005, "End-of-data detected")
51 SENSE_CODE(0x0409, "Logical unit not ready, self-test in progress")
64 SENSE_CODE(0x0417, "Logical unit not ready, calibration required")
87 SENSE_CODE(0x0801, "Logical unit communication time-out")
89 SENSE_CODE(0x0803, "Logical unit communication CRC error (Ultra-DMA/32)")
102 SENSE_CODE(0x0B01, "Warning - specified temperature exceeded")
[all …]
/linux/drivers/iio/light/
H A Dcros_ec_light_prox.c1 // SPDX-License-Identifier: GPL-2.0
3 * cros_ec_light_prox - Driver for light and prox sensors behing CrosEC.
47 int idx = chan->scan_index; in cros_ec_light_prox_read()
49 mutex_lock(&st->core.cmd_lock); in cros_ec_light_prox_read()
53 if (chan->type == IIO_PROXIMITY) { in cros_ec_light_prox_read()
61 ret = -EINVAL; in cros_ec_light_prox_read()
65 if (chan->type == IIO_LIGHT) { in cros_ec_light_prox_read()
72 * pre-processed and represents the ambient light in cros_ec_light_prox_read()
78 ret = -EINVAL; in cros_ec_light_prox_read()
82 st->core.param.cmd = MOTIONSENSE_CMD_SENSOR_OFFSET; in cros_ec_light_prox_read()
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/linux/drivers/net/wireless/ath/ath5k/
H A Deeprom.c2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
49 if (ee->ee_version > AR5K_EEPROM_VERSION_3_2) in ath5k_eeprom_bin2freq()
52 val = bin > 62 ? (10 * 62) + (5 * (bin - 62)) + 5100 : in ath5k_eeprom_bin2freq()
55 if (ee->ee_version > AR5K_EEPROM_VERSION_3_2) in ath5k_eeprom_bin2freq()
75 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_eeprom_init_header()
89 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_0) in ath5k_eeprom_init_header()
101 eep_max = (eep_max | val) - AR5K_EEPROM_INFO_BASE; in ath5k_eeprom_init_header()
114 return -EIO; in ath5k_eeprom_init_header()
[all …]
/linux/drivers/phy/mediatek/
H A Dphy-mtk-tphy.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/phy/phy.h>
15 #include <linux/nvmem-consumer.h>
22 #include "phy-mtk-io.h"
24 /* version V1 sub-banks offset base address */
35 /* version V2/V3 sub-banks offset base address */
218 /* CDR Charge Pump P-path current adjustment */
237 /* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */
246 /* I-path capacitance adjustment for Gen1 */
279 * mtk_phy_pdata - SoC specific platform data
[all …]
/linux/drivers/platform/x86/
H A Dapple-gmux.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2010-2012 Andreas Heider <andreas@meetr.de>
19 #include <linux/apple-gmux.h>
32 * A `Lattice XP2`_ on pre-retinas, a `Renesas R4F2113`_ on pre-T2 retinas.
41 * dual GPUs but no built-in display.)
45 * to access a pre-retina gmux are infixed ``_pio_``, those for a pre-T2
54 * https://www.nxp.com/docs/en/data-sheet/PCAL6524.pdf
112 return inb(gmux_data->iostart + port); in gmux_pio_read8()
118 outb(val, gmux_data->iostart + port); in gmux_pio_write8()
123 return inl(gmux_data->iostart + port); in gmux_pio_read32()
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/linux/drivers/net/wireless/ralink/rt2x00/
H A Drt2500usb.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
36 * Default offset is required for RSSI <-> dBm conversion.
238 * ACK_TIMEOUT: ACK Timeout in unit of 1-us.
315 * TXRX_CSR9: TX ACK time-out.
350 * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
498 * BBP pre-TX registers.
499 * PHY_CSR5: BBP pre-TX CCK.
506 * BBP pre-TX registers.
507 * PHY_CSR6: BBP pre-TX OFDM.
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/linux/sound/soc/codecs/
H A Drt1318.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt1318.h -- Platform data for RT1318
100 /* Clock-1 (0xC001) */
119 /* Clock-2 (0xC003) */
132 /* Clock-3 (0xC004) */
148 /* Clock-4 (0xC005) */
163 /* Clock-5 (0xC006) */
176 /* Clock-6 (0xC007) */
315 /* R0 calibration result */
322 /* PLL pre-defined M/N/K */
/linux/drivers/thermal/qcom/
H A Dtsens.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/nvmem-consumer.h>
26 * struct tsens_irq_data - IRQ status and temperature violations
81 if (priv->num_sensors > MAX_SENSORS) in tsens_read_calibration()
82 return -EINVAL; in tsens_read_calibration()
88 ret = nvmem_cell_read_variable_le_u32(priv->dev, name, &mode); in tsens_read_calibration()
89 if (ret == -ENOENT) in tsens_read_calibration()
90 dev_warn(priv->dev, "Please migrate to separate nvmem cells for calibration data\n"); in tsens_read_calibration()
94 dev_dbg(priv->dev, "calibration mode is %d\n", mode); in tsens_read_calibration()
100 ret = nvmem_cell_read_variable_le_u32(priv->dev, name, &base1); in tsens_read_calibration()
[all …]
/linux/drivers/net/wireless/intel/iwlegacy/
H A Dcommon.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
8 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
31 #define IL_ERR(f, a...) dev_err(&il->pci_dev->dev, f, ## a)
32 #define IL_WARN(f, a...) dev_warn(&il->pci_dev->dev, f, ## a)
33 #define IL_WARN_ONCE(f, a...) dev_warn_once(&il->pci_dev->dev, f, ## a)
34 #define IL_INFO(f, a...) dev_info(&il->pci_dev->dev, f, ## a)
46 #define U32_PAD(n) ((4-(n))&0x3)
48 /* CT-KILL constants */
56 * Use default noise value of -127 ... this is below the range of measurable
[all …]
/linux/Documentation/hwmon/
H A Dasc7621.rst20 Andigilog has both the PECI and pre-PECI versions of the Heceta-6, as
21 Intel calls them. Heceta-6e has high frequency PWM and Heceta-6p has
23 Heceta-6e part and aSC7621 is the Heceta-6p part. They are both in
28 have used registers below 20h for vendor-specific functions in addition
29 to those in the Intel-specified vendor range.
32 The fan speed control uses this finer value to produce a "step-less" fan
33 PWM output. These two bytes are "read-locked" to guarantee that once a
34 high or low byte is read, the other byte is locked-in until after the
37 sheet says 10-bits of resolution, although you may find the lower bits
47 We offer GPIO features on the former VID pins. These are open-drain
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