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/linux/arch/arm64/boot/dts/apple/
H A Dt600x-pmgr.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * PMGR Power domains for the Apple T6001 "M1 Max" SoC
9 DIE_NODE(ps_pms_bridge): power-controller@100 {
10 compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
12 #power-domain-cells = <0>;
13 #reset-cells = <0>;
15 apple,always-on; /* Core device */
18 DIE_NODE(ps_aic): power-controller@108 {
19 compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
21 #power-domain-cells = <0>;
[all …]
H A Dt8112-pmgr.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * PMGR Power domains for the Apple T8112 "M2" SoC
10 ps_sbr: power-controller@100 {
11 compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";
13 #power-domain-cells = <0>;
14 #reset-cells = <0>;
16 apple,always-on; /* Core device */
19 ps_aic: power-controller@108 {
20 compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";
22 #power-domain-cells = <0>;
[all …]
H A Dt8103-pmgr.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * PMGR Power domains for the Apple T8103 "M1" SoC
10 ps_sbr: power-controller@100 {
11 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
13 #power-domain-cells = <0>;
14 #reset-cells = <0>;
16 apple,always-on; /* Core device */
19 ps_aic: power-controller@108 {
20 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
22 #power-domain-cells = <0>;
[all …]
H A Dt8015-pmgr.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * PMGR Power domains for the Apple T8015 "A11" SoC
9 ps_cpu0: power-controller@80000 {
10 compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";
12 #power-domain-cells = <0>;
13 #reset-cells = <0>;
15 apple,always-on; /* Core device */
18 ps_cpu1: power-controller@80008 {
19 compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";
21 #power-domain-cells = <0>;
[all …]
H A Dt8012-pmgr.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * PMGR Power domains for the Apple T8012 "T2" SoC
9 ps_cpu0: power-controller@80000 {
10 compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";
12 #power-domain-cells = <0>;
13 #reset-cells = <0>;
15 apple,always-on; /* Core device */
18 ps_cpu1: power-controller@80008 {
19 compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";
21 #power-domain-cells = <0>;
[all …]
H A Dt8011-pmgr.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * PMGR Power domains for the Apple T8011 "A10X" SoC
9 ps_cpu0: power-controller@80000 {
10 compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";
12 #power-domain-cells = <0>;
13 #reset-cells = <0>;
15 apple,always-on; /* Core device */
18 ps_cpu1: power-controller@80008 {
19 compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";
21 #power-domain-cells = <0>;
[all …]
H A Ds8001-pmgr.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * PMGR Power domains for the Apple S8001 "A9X" SoC
9 ps_cpu0: power-controller@80000 {
10 compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";
12 #power-domain-cells = <0>;
13 #reset-cells = <0>;
15 apple,always-on; /* Core device */
18 ps_cpu1: power-controller@80008 {
19 compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";
21 #power-domain-cells = <0>;
[all …]
H A Ds5l8960x-pmgr.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * PMGR Power domains for the Apple S5L8960X "A7" SoC
9 ps_cpu0: power-controller@20000 {
10 compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";
12 #power-domain-cells = <0>;
13 #reset-cells = <0>;
15 apple,always-on; /* Core device */
18 ps_cpu1: power-controller@20008 {
19 compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";
21 #power-domain-cells = <0>;
[all …]
H A Dt7001-pmgr.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * PMGR Power domains for the Apple T7001 "A8X" SoC
9 ps_cpu0: power-controller@20000 {
10 compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";
12 #power-domain-cells = <0>;
13 #reset-cells = <0>;
15 apple,always-on; /* Core device */
18 ps_cpu1: power-controller@20008 {
19 compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";
21 #power-domain-cells = <0>;
[all …]
H A Dt8010-pmgr.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * PMGR Power domains for the Apple T8010 "A10" SoC
9 ps_cpu0: power-controller@80000 {
10 compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";
12 #power-domain-cells = <0>;
13 #reset-cells = <0>;
15 apple,always-on; /* Core device */
18 ps_cpu1: power-controller@80008 {
19 compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";
21 #power-domain-cells = <0>;
[all …]
H A Ds800-0-3-pmgr.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * PMGR Power domains for the Apple S8000/3 "A9" SoC
9 ps_cpu0: power-controller@80000 {
10 compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";
12 #power-domain-cells = <0>;
13 #reset-cells = <0>;
15 apple,always-on; /* Core device */
18 ps_cpu1: power-controller@80008 {
19 compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";
21 #power-domain-cells = <0>;
[all …]
H A Dt7000-pmgr.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * PMGR Power domains for the Apple T7000 "A8" SoC
8 ps_cpu0: power-controller@20000 {
9 compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";
11 #power-domain-cells = <0>;
12 #reset-cells = <0>;
14 apple,always-on; /* Core device */
17 ps_cpu1: power-controller@20008 {
18 compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";
20 #power-domain-cells = <0>;
[all …]
/linux/drivers/power/reset/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 bool "Board level reset or power off"
5 Provides a number of drivers which either reset a complete board
6 or shut it down, by manipulating the main power supply on the board.
8 Say Y here to enable board reset and power off
13 bool "ams AS3722 power-off driver"
14 depends on MFD_AS3722
16 This driver supports turning off board via a ams AS3722 power-off.
20 depends on ARCH_AT91
27 tristate "Atmel AT91 reset driver"
[all …]
/linux/Documentation/ABI/stable/
H A Dsysfs-driver-mlxreg-io1 What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/asic_health
6 0 - health failed, 2 - health OK, 3 - ASIC in booting state.
10 What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld1_version
11 What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld2_version
16 on carrier and switch boards.
20 What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/fan_dir
25 forward direction - relevant bit is set 0;
26 reversed direction - relevant bit is set 1.
30 What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld3_version
35 on LED or Gearbox board.
[all …]
/linux/Documentation/devicetree/bindings/clock/ti/davinci/
H A Dpsc.txt1 Binding for TI DaVinci Power Sleep Controller (PSC)
3 The PSC provides power management, clock gating and reset functionality. It is
7 - compatible: shall be one of:
8 - "ti,da850-psc0" for PSC0 on DA850/OMAP-L138/AM18XX
9 - "ti,da850-psc1" for PSC1 on DA850/OMAP-L138/AM18XX
10 - reg: physical base address and size of the controller's register area
11 - #clock-cells: from common clock binding; shall be set to 1
12 - #power-domain-cells: from generic power domain binding; shall be set to 1.
13 - clocks: phandles to clocks corresponding to the clock-names property
14 - clock-names: list of parent clock names - depends on compatible value
[all …]
/linux/Documentation/devicetree/bindings/mfd/
H A Drohm,bd71847-pmic.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mfd/rohm,bd71847-pmic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ROHM BD71847 and BD71850 Power Management Integrated Circuit
10 - Matti Vaittinen <mazziesaccount@gmail.com>
13 BD71847AMWV and BD71850MWV are programmable Power Management ICs for powering
14 single-core, dual-core, and quad-core SoCs such as NXP-i.MX 8M. It is
18 …s://www.rohm.com/products/power-management/power-management-ic-for-system/industrial-consumer-appl…
19 …s://www.rohm.com/products/power-management/power-management-ic-for-system/industrial-consumer-appl…
[all …]
H A Dtwl4030-power.txt1 Texas Instruments TWL family (twl4030) reset and power management module
3 The power management module inside the TWL family provides several facilities
4 to control the power resources, including power scripts. For now, the
8 - compatible : must be one of the following
9 "ti,twl4030-power"
10 "ti,twl4030-power-reset"
11 "ti,twl4030-power-idle"
12 "ti,twl4030-power-idle-osc-off"
14 The use of ti,twl4030-power-reset is recommended at least on
15 3530 that needs a special configuration for warm reset to work.
[all …]
/linux/arch/sparc/include/asm/
H A Dfhc.h1 /* SPDX-License-Identifier: GPL-2.0 */
14 #define CLOCK_PWRSTAT 0x30UL /* Power status */
15 #define CLOCK_PWRPRES 0x40UL /* Power presence */
18 #define CLOCK_PWRSTAT2 0x70UL /* Power status two */
20 #define CLOCK_CTRL_LLED 0x04 /* Left LED, 0 == on */
21 #define CLOCK_CTRL_MLED 0x02 /* Mid LED, 1 == on */
22 #define CLOCK_CTRL_RLED 0x01 /* RIght LED, 1 == on */
30 #define FHC_PREGS_RCS 0x10UL /* FHC Reset Control/Status Register */
31 #define FHC_RCS_POR 0x80000000 /* Last reset was a power cycle */
32 #define FHC_RCS_SPOR 0x40000000 /* Last reset was sw power on reset */
[all …]
/linux/Documentation/devicetree/bindings/pci/
H A Dnvidia,tegra194-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
15 This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus
16 inherits all the common properties defined in snps,dw-pcie-ep.yaml. Some
20 On Tegra194, controllers C0, C4 and C5 support Endpoint mode.
[all …]
/linux/Documentation/driver-api/usb/
H A Dpersist.rst1 .. _usb-persist:
14 bus must continue to supply suspend current (around 1-5 mA). This
16 detect connect-change events (devices being plugged in or unplugged).
17 The technical term is "power session".
19 If a USB device's power session is interrupted then the system is
27 controller loses power during a system suspend, then when the system
35 system woke up, who cares? It'll still work the same when you type on
38 Unfortunately problems _can_ arise, particularly with mass-storage
41 filesystem on the device, you're out of luck -- everything in that
43 root filesystem was located on the device, since your system will
[all …]
/linux/drivers/pmdomain/bcm/
H A Dbcm2835-power.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Power domain driver for Broadcom BCM2835
8 #include <dt-bindings/soc/bcm2835-pm.h>
12 #include <linux/mfd/bcm2835-pm.h>
16 #include <linux/reset-controller.h>
61 /* The power gates must be enabled with this bit before enabling the LDO in the
109 #define PM_READ(reg) readl(power->base + (reg))
110 #define PM_WRITE(reg, val) writel(PM_PASSWORD | (val), power->base + (reg))
133 struct bcm2835_power *power; member
149 struct reset_controller_dev reset; member
[all …]
/linux/arch/arm/mach-meson/
H A Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
13 #include <linux/reset.h>
23 #define MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(c) (0x04 + ((c - 1) << 2))
31 #define MESON_CPU_PWR_A9_MEM_PD0_M(c) (0x0f << (32 - (c * 4)))
106 meson_smp_prepare_cpus("arm,cortex-a5-scu", "amlogic,meson8b-pmu", in meson8b_smp_prepare_cpus()
107 "amlogic,meson8b-smp-sram"); in meson8b_smp_prepare_cpus()
112 meson_smp_prepare_cpus("arm,cortex-a9-scu", "amlogic,meson8-pmu", in meson8_smp_prepare_cpus()
113 "amlogic,meson8-smp-sram"); in meson8_smp_prepare_cpus()
119 * Set the entry point before powering on the CPU through the SCU. This in meson_smp_begin_secondary_boot()
121 * system without power-cycling, or when taking the CPU offline and in meson_smp_begin_secondary_boot()
[all …]
/linux/kernel/
H A Dcpu_pm.c1 // SPDX-License-Identifier: GPL-2.0-only
53 * cpu_pm_register_notifier - register a driver with cpu_pm
57 * CPU and CPU cluster low power entry and exit.
74 * cpu_pm_unregister_notifier - unregister a driver with cpu_pm
94 * cpu_pm_enter - CPU low power entry notifier
96 * Notifies listeners that a single CPU is entering a low power state that may
97 * cause some blocks in the same power domain as the cpu to reset.
99 * Must be called on the affected CPU with interrupts disabled. Platform is
100 * responsible for ensuring that cpu_pm_enter is not called twice on the same
102 * co-processor, interrupt controller and its PM extensions, local CPU
[all …]
/linux/arch/arm/mach-sa1100/include/mach/
H A Dassabet.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/arm/mach-sa1100/include/mach/assabet.h
8 * Only include this file from SA1100-specific files.
26 #define ASSABET_SCR_INIT -1
41 #define ASSABET_BCR_CF_PWR (1<<0) /* Compact Flash Power (1 = 3.3v, 0 = off) */
42 #define ASSABET_BCR_CF_RST (1<<1) /* Compact Flash Reset (1 = power up reset) */
43 #define ASSABET_BCR_NGFX_RST (1<<1) /* Graphics Accelerator Reset (0 = hold reset) */
44 #define ASSABET_BCR_NCODEC_RST (1<<2) /* 0 = Holds UCB1300, ADI7171, and UDA1341 in reset */
46 #define ASSABET_BCR_IRDA_MD0 (1<<4) /* Range/Power select */
47 #define ASSABET_BCR_IRDA_MD1 (1<<5) /* Range/Power select */
[all …]
/linux/Documentation/devicetree/bindings/arm/keystone/
H A Dti,sci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI-SCI controller
10 - Nishanth Menon <nm@ti.com>
15 management of the System on Chip (SoC) system. These include various system
19 block called Power Management Micro Controller (PMMC). This hardware block is
21 on multiple processors including ones running Linux.
23 See https://software-dl.ti.com/tisci/esd/latest/index.html for protocol definition.
25 The TI-SCI node describes the Texas Instrument's System Controller entity node.
[all …]

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