| /freebsd/lib/libpmc/pmu-events/arch/arm64/fujitsu/a64fx/ |
| H A D | pipeline.json | 9 "PublicDescription": "This event counts valid cycles of EAGA pipeline.",
12 "BriefDescription": "This event counts valid cycles of EAGA pipeline."
15 "PublicDescription": "This event counts valid cycles of EAGB pipeline.",
18 "BriefDescription": "This event counts valid cycles of EAGB pipeline."
21 "PublicDescription": "This event counts valid cycles of EXA pipeline.",
24 "BriefDescription": "This event counts valid cycles of EXA pipeline."
27 "PublicDescription": "This event counts valid cycles of EXB pipeline.",
30 "BriefDescription": "This event counts valid cycles of EXB pipeline."
33 "PublicDescription": "This event counts valid cycles of FLA pipeline.",
36 "BriefDescription": "This event counts valid cycles of FLA pipeline."
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCScheduleP10.td | 12 // Modeling pipeline forwarding logic.
40 // Pipeline Groups
83 // A BF pipeline may take from 7 to 36 cycles to complete.
84 // Some BF operations may keep the pipeline busy for up to 10 cycles.
114 // A BR pipeline may take 2 cycles to complete.
119 // A CY pipeline may take 7 cycles to complete.
124 // A DF pipeline may take from 13 to 174 cycles to complete.
125 // Some DF operations may keep the pipeline busy for up to 67 cycles.
210 // A DV pipeline may take from 20 to 83 cycles to complete.
211 // Some DV operations may keep the pipeline bus
[all...] |
| H A D | PPCSchedule440.td | 13 // The basic PPC 440 does not include a floating-point unit; the pipeline
34 // the complex integer (I-pipe) pipeline
36 // the floating-point execution (F-pipe) pipeline
37 def P440_IEXE1 : FuncUnit; // Execution stage 1 for the I pipeline
38 def P440_IEXE2 : FuncUnit; // Execution stage 2 for the I pipeline
39 def P440_IWB : FuncUnit; // Write-back unit for the I pipeline
40 def P440_JEXE1 : FuncUnit; // Execution stage 1 for the J pipeline
41 def P440_JEXE2 : FuncUnit; // Execution stage 2 for the J pipeline
42 def P440_JWB : FuncUnit; // Write-back unit for the J pipeline
43 def P440_AGEN : FuncUnit; // Address generation for the L pipeline
[all …]
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| H A D | PPCScheduleP7.td | 113 // Instruction of BRU pipeline
136 // Instructions of CRU pipeline
240 // Instructions of FPU and VMX pipeline
|
| /freebsd/contrib/llvm-project/llvm/tools/opt/ |
| H A D | NewPMDriver.cpp | 83 // This flag specifies a textual description of the alias analysis pipeline to
87 AAPipeline("aa-pipeline",
89 "pipeline for handling managed aliasing queries"),
92 /// {{@ These options accept textual pipeline descriptions which will be
96 cl::desc("A textual description of the function pass pipeline inserted at "
102 "A textual description of the loop pass pipeline inserted at "
107 cl::desc("A textual description of the loop pass pipeline inserted at "
112 cl::desc("A textual description of the function pass pipeline inserted at "
117 cl::desc("A textual description of the cgscc pass pipeline inserted at "
122 cl::desc("A textual description of the function pass pipeline inserted at "
[all …]
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| /freebsd/contrib/llvm-project/llvm/include/llvm/MCA/ |
| H A D | Pipeline.h | 1 //===--------------------- Pipeline.h ---------------------------*- C++ -*-===//
11 /// pipeline of a hardware backend.
26 /// A pipeline for a specific subtarget.
41 /// of the instruction pipeline.
43 /// The Pipeline entry point is method 'run()' which executes cycles in a loop
47 /// Internally, the Pipeline collects statistical information in the form of
50 class Pipeline {
51 Pipeline(const Pipeline &P) = delete;
52 Pipeline &operator=(const Pipeline &P) = delete;
55 Created, // Pipeline was just created. The default state.
[all …]
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| H A D | Context.h | 12 /// a default out-of-order pipeline with fetch, dispatch, execute, and retire
24 #include "llvm/MCA/Pipeline.h"
32 /// the pre-built "default" out-of-order pipeline.
68 /// Construct a basic pipeline for simulating an out-of-order pipeline.
69 /// This pipeline consists of Fetch, Dispatch, Execute, and Retire stages.
70 std::unique_ptr<Pipeline> createDefaultPipeline(const PipelineOptions &Opts,
74 /// Construct a basic pipeline for simulating an in-order pipeline.
75 /// This pipeline consists of Fetch, InOrderIssue, and Retire stages.
76 std::unique_ptr<Pipeline> createInOrderPipeline(const PipelineOptions &Opts,
|
| H A D | HWEventListener.h | 30 // generic subtarget-agnostic classes (e.g., Pipeline, HWInstructionEvent,
34 // emitted by subtarget-specific pipeline stages (e.g., ExecuteStage,
107 // A HWStallEvent represents a pipeline stall caused by the lack of hardware
135 // the presence of data dependencies or unavailability of pipeline resources.
141 // pipeline resources were unavailable.
165 // Generic events generated by the pipeline.
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/Passes/ |
| H A D | PassBuilder.h | 46 /// Constructor sets pipeline tuning defaults based on cl::opts. Each option
80 // Add LTO pipeline tuning option to enable the unified LTO pipeline.
113 /// A struct to capture parsed pass pipeline names.
115 /// A pipeline is defined as a series of names, each of which may in itself
116 /// recursively contain a nested pipeline. A name is either the name of a pass
117 /// (e.g. "instcombine") or the name of a pipeline type (e.g. "cgscc"). If the
120 /// detailed description of the textual pipeline format.
181 /// pipeline.
183 /// This is a long pipeline and uses most of the per-function optimization
199 /// pipeline.
[all …]
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| /freebsd/sys/contrib/openzfs/include/sys/ |
| H A D | zio_impl.h | 39 * XXX -- Describe ZFS I/O pipeline here. Fill in as needed.
41 * The ZFS I/O pipeline is comprised of various stages which are defined
54 * Although the most common pipeline are used by the basic I/O operations
59 * Interlock Pipeline:
60 * The interlock pipeline is the most basic pipeline and is used by all
61 * of the I/O operations. The interlock pipeline does not perform any I/O
65 * Vdev child Pipeline:
66 * The vdev child pipeline is responsible for performing the physical I/O.
67 * It is in this pipeline where the I/O are queued and possibly cached.
69 * In addition to performing I/O, the pipeline is also responsible for
[all …]
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| /freebsd/contrib/llvm-project/llvm/include/llvm/DebugInfo/CodeView/ |
| H A D | TypeVisitorCallbackPipeline.h | 26 for (auto *Visitor : Pipeline) { in visitUnknownType()
34 for (auto *Visitor : Pipeline) { in visitUnknownMember()
42 for (auto *Visitor : Pipeline) { in visitTypeBegin()
50 for (auto *Visitor : Pipeline) { in visitTypeBegin()
58 for (auto *Visitor : Pipeline) { in visitTypeEnd()
66 for (auto *Visitor : Pipeline) { in visitMemberBegin()
74 for (auto *Visitor : Pipeline) { in visitMemberEnd()
82 Pipeline.push_back(&Callbacks); in addCallbackToPipeline()
100 for (auto *Visitor : Pipeline) { in visitKnownRecordImpl()
109 for (auto *Visitor : Pipeline) { in visitKnownMemberImpl()
[all …]
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| H A D | SymbolVisitorCallbackPipeline.h | 25 for (auto *Visitor : Pipeline) { in visitUnknownSymbol()
33 for (auto *Visitor : Pipeline) { in visitSymbolBegin()
41 for (auto *Visitor : Pipeline) { in visitSymbolBegin()
49 for (auto *Visitor : Pipeline) { in visitSymbolEnd()
57 Pipeline.push_back(&Callbacks); in addCallbackToPipeline()
62 for (auto Visitor : Pipeline) { \
72 std::vector<SymbolVisitorCallbacks *> Pipeline;
|
| /freebsd/contrib/llvm-project/llvm/lib/MCA/ |
| H A D | Pipeline.cpp | 1 //===--------------------- Pipeline.cpp -------------------------*- C++ -*-===//
11 /// pipeline of a hardware backend.
15 #include "llvm/MCA/Pipeline.h"
24 void Pipeline::addEventListener(HWEventListener *Listener) { in addEventListener()
31 bool Pipeline::hasWorkToProcess() { in hasWorkToProcess()
37 Expected<unsigned> Pipeline::run() { in run()
38 assert(!Stages.empty() && "Unexpected empty pipeline found!"); in run()
52 Error Pipeline::runCycle() { in runCycle()
86 void Pipeline::appendStage(std::unique_ptr<Stage> S) { in appendStage()
96 void Pipeline::notifyCycleBegin() { in notifyCycleBegin()
[all …]
|
| H A D | Context.cpp | 12 /// a default out-of-order pipeline with fetch, dispatch, execute, and retire
31 std::unique_ptr<Pipeline>
46 // Create the pipeline stages. in createDefaultPipeline()
60 // Build the pipeline. in createDefaultPipeline()
61 auto StagePipeline = std::make_unique<Pipeline>(); in createDefaultPipeline()
72 std::unique_ptr<Pipeline>
80 // Create the pipeline stages. in createInOrderPipeline()
83 auto StagePipeline = std::make_unique<Pipeline>(); in createInOrderPipeline()
89 // Build the pipeline. in createInOrderPipeline()
|
| /freebsd/contrib/llvm-project/llvm/lib/Passes/ |
| H A D | PassBuilder.cpp | 328 "print-pipeline-passes",
329 cl::desc("Print a '-passes' compatible string describing the pipeline "
492 // We almost always want the default alias analysis pipeline. in registerFunctionAnalyses()
1212 /// Tests whether a pass name starts with a valid prefix for a default pipeline
1221 /// When parsing a pipeline text, the type of the outermost pipeline may be
1240 // Manually handle aliases for pre-configured pipeline fragments. in isModulePassName()
1392 std::vector<PipelineElement> &Pipeline = *PipelineStack.back(); in parsePipelineText() local
1394 Pipeline.push_back({Text.substr(0, Pos), {}}); in parsePipelineText()
1407 // Push the inner pipeline onto the stack to continue processing. in parsePipelineText()
1408 PipelineStack.push_back(&Pipeline.back().InnerPipeline); in parsePipelineText()
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/display/ |
| H A D | arm,komeda.txt | 18 Required properties for sub-node: pipeline@nq
19 Each device contains one or two pipeline sub-nodes (at least one), each
20 pipeline node should provide properties:
21 - reg: Zero-indexed identifier for the pipeline
27 - port: each pipeline connect to an encoder input port. The connection is
53 dp0_pipe0: pipeline@0 {
65 dp0_pipe1: pipeline@1 {
|
| H A D | arm,komeda.yaml | 15 to a 4K resolution each. Each pipeline can be composed of up to four
59 '^pipeline@[01]$':
90 - pipeline@0
107 dp0_pipe0: pipeline@0 {
119 dp0_pipe1: pipeline@1 {
|
| H A D | allwinner,sun4i-a10-display-engine.yaml | 7 title: Allwinner A10 Display Engine Pipeline
14 The display engine pipeline (and its entry point, since it can be
18 The Allwinner A10 Display pipeline is composed of several components
22 display pipeline, when there are multiple components of the same
35 For a two pipeline system such as the one depicted above, the lines
|
| H A D | simple-framebuffer.yaml | 129 allwinner,pipeline:
130 description: Pipeline used by the framebuffer on Allwinner SoCs
145 amlogic,pipeline:
146 description: Pipeline used by the framebuffer on Amlogic SoCs
172 - allwinner,pipeline
182 - amlogic,pipeline
200 allwinner,pipeline = "de_be0-lcd0";
|
| /freebsd/usr.bin/man/ |
| H A D | man.sh | 343 local IFS pipeline testline
380 pipeline="mandoc -Tps $mandoc_args"
382 pipeline="mandoc $mandoc_args | $MANPAGER"
398 decho "Command: $cattool \"$manpage\" | eval \"$pipeline\""
401 $cattool "$manpage" | eval "$pipeline"
410 local IFS l nroff_dev pipeline preproc_arg tool
414 # setup the pipeline of commands based on the user's request.
469 e) pipeline="$pipeline | $EQN" ;;
471 p) pipeline="$pipeline | $PIC" ;;
472 r) pipeline="$pipeline | $REFER" ;;
[all …]
|
| /freebsd/tools/tools/netrate/juggle/ |
| H A D | juggle.c | 233 juggle(int fd1, int fd2, int pipeline) in juggle() argument
243 for (j = 0; j < pipeline; j++) { in juggle()
248 for (j = 0; j < pipeline; j++) { in juggle()
256 for (j = 0; j < pipeline; j++) { in juggle()
315 thread_juggle(int fd1, int fd2, int pipeline) in thread_juggle() argument
321 threaded_pipeline = pipeline; in thread_juggle()
344 for (j = 0; j < pipeline; j++) { in thread_juggle()
349 for (j = 0; j < pipeline; j++) { in thread_juggle()
374 process_juggle(int fd1, int fd2, int pipeline) in process_juggle() argument
395 for (j = 0; j < pipeline; j++) { in process_juggle()
[all …]
|
| /freebsd/sbin/hastd/ |
| H A D | hast_proto.c | 67 static struct hast_pipe_stage pipeline[] = { variable
95 for (ii = 0; ii < sizeof(pipeline) / sizeof(pipeline[0]); in hast_proto_send()
97 (void)pipeline[ii].hps_send(res, nv, &dptr, &size, in hast_proto_send()
197 for (ii = sizeof(pipeline) / sizeof(pipeline[0]); ii > 0; in hast_proto_recv_data()
199 ret = pipeline[ii - 1].hps_recv(res, nv, &dptr, in hast_proto_recv_data()
|
| /freebsd/contrib/llvm-project/llvm/lib/DebugInfo/CodeView/ |
| H A D | CVTypeVisitor.cpp | 190 Visitor((Source == VDS_BytesPresent) ? Pipeline : Callbacks) { in FieldListVisitHelper()
192 Pipeline.addCallbackToPipeline(Deserializer); in FieldListVisitHelper()
193 Pipeline.addCallbackToPipeline(Callbacks); in FieldListVisitHelper()
200 TypeVisitorCallbackPipeline Pipeline; member
206 : Visitor((Source == VDS_BytesPresent) ? Pipeline : Callbacks) { in VisitHelper()
208 Pipeline.addCallbackToPipeline(Deserializer); in VisitHelper()
209 Pipeline.addCallbackToPipeline(Callbacks); in VisitHelper()
214 TypeVisitorCallbackPipeline Pipeline; member
|
| /freebsd/lib/libpmc/pmu-events/arch/x86/jaketown/ |
| H A D | jkt-metrics.json | 21 …e uops that do not eventually get retired and slots for which the issue-pipeline was blocked due t…
28 …e uops that do not eventually get retired and slots for which the issue-pipeline was blocked due t…
50 … useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be at…
57 … useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be at…
68 "MetricGroup": "Pipeline;Ret;Retire",
74 "MetricGroup": "Pipeline;Mem",
80 "MetricGroup": "Pipeline",
84 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
90 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
98 "MetricGroup": "Cor;Pipeline",
[all …]
|
| /freebsd/lib/libpmc/pmu-events/arch/x86/sandybridge/ |
| H A D | snb-metrics.json | 21 …e uops that do not eventually get retired and slots for which the issue-pipeline was blocked due t…
28 …e uops that do not eventually get retired and slots for which the issue-pipeline was blocked due t…
50 … useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be at…
57 … useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be at…
68 "MetricGroup": "Pipeline;Ret;Retire",
74 "MetricGroup": "Pipeline;Mem",
80 "MetricGroup": "Pipeline",
84 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
90 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
98 "MetricGroup": "Cor;Pipeline",
[all …]
|