Home
last modified time | relevance | path

Searched full:pin (Results 1 – 25 of 2839) sorted by relevance

12345678910>>...114

/linux/arch/arm/boot/dts/microchip/
H A Dsama5d3_lcd.dtsi60 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
61 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
62 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
63 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
64 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
65 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
66 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
67 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
68 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
69 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
[all …]
H A Dat91sam9x5_lcd.dtsi63 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
64 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
65 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
66 AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
67 AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
68 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
69 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
70 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
71 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
72 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
[all …]
/linux/arch/arm64/boot/dts/exynos/
H A Dexynosautov9-pinctrl.dtsi3 * Samsung's ExynosAutov9 SoC pin-mux and pin-config device tree source
7 * Samsung's ExynosAutov9 SoC pin-mux and pin-config options are listed as
42 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
47 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
60 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
61 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
66 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
67 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
106 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
107 samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
[all …]
H A Dexynos7870-pinctrl.dtsi3 * Samsung Exynos7870 SoC pin-mux and pin-config device tree source
81 samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
82 samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
83 samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>;
84 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
89 samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
90 samsung,pin-con-pdn = <EXYNOS_PIN_PDN_INPUT>;
91 samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>;
92 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
97 samsung,pin-function = <EXYNOS_PIN_FUNC_6>;
[all …]
H A Dexynos7885-pinctrl.dtsi3 * Samsung Exynos7885 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos7885 SoC pin-mux and pin-config options are listed as
84 samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
85 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
90 samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
91 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
96 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
97 samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
98 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
99 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
[all …]
H A Dexynosautov920-pinctrl.dtsi3 * Samsung's ExynosAutov920 SoC pin-mux and pin-config device tree source
7 * Samsung's ExynosAutov920 SoC pin-mux and pin-config options are listed as
182 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
183 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
184 samsung,pin-con-pdn = <EXYNOS_PIN_PULL_NONE>;
189 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
190 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
191 samsung,pin-con-pdn = <EXYNOS_PIN_PULL_DOWN>;
196 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
197 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
[all …]
H A Dexynos7-pinctrl.dtsi3 * Samsung's Exynos7 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos7 SoC pin-mux and pin-config options are listed as
189 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
190 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
191 samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
196 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
197 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
198 samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
203 samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
204 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Ds5pv210-pinctrl.dtsi3 * Samsung's S5PV210 SoC device tree source - pin control-related
11 * Samsung's S5PV210 SoC pin banks, pin-mux and pin-config options are
18 pin- ## _pin { \
20 samsung,pin-con-pdn = <S5PV210_PIN_PDN_ ##_mode>; \
21 samsung,pin-pud-pdn = <S5PV210_PIN_PULL_ ##_pull>; \
279 samsung,pin-function = <S5PV210_PIN_FUNC_2>;
280 samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
281 samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
286 samsung,pin-function = <S5PV210_PIN_FUNC_2>;
287 samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
[all …]
H A Dexynos4x12-pinctrl.dtsi3 * Samsung's Exynos4x12 SoCs pin-mux and pin-config device tree source
8 * Samsung's Exynos4x12 SoCs pin-mux and pin-config options are listed as device
15 pin- ## _pin { \
17 samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \
18 samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_ ##_pull>; \
128 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
129 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
130 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
135 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
136 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
[all …]
H A Dexynos4210-pinctrl.dtsi3 * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source
10 * Samsung's Exynos4210 SoC pin-mux and pin-config options are listed as device
147 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
148 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
149 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
154 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
155 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
156 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
161 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
162 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
[all …]
H A Dexynos5250-pinctrl.dtsi3 * Samsung's Exynos5250 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5250 SoC pin-mux and pin-config options are listed as device
202 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
203 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
204 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
209 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
210 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
211 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
216 samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
217 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
[all …]
H A Dexynos3250-pinctrl.dtsi3 * Samsung's Exynos3250 SoCs pin-mux and pin-config device tree source
8 * Samsung's Exynos3250 SoCs pin-mux and pin-config options are listed as device
15 pin- ## _pin { \
17 samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; \
18 samsung,pin-pud = <EXYNOS_PIN_PULL_ ##_pull>; \
19 samsung,pin-drv = <EXYNOS4_PIN_DRV_ ##_drv>; \
23 pin- ## _pin { \
25 samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \
26 samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_ ##_pull>; \
88 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
[all …]
H A Dexynos5420-pinctrl.dtsi3 * Samsung's Exynos5420 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5420 SoC pin-mux and pin-config options are listed as device
63 samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
64 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
65 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
70 samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
71 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
72 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
162 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
163 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
[all …]
H A Ds3c64xx-pinctrl.dtsi4 * - pin control-related definitions
8 * Samsung's S3C64xx SoCs pin banks, pin-mux and pin-config options are
16 * Pin banks
131 * Pin groups
136 samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
137 samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
142 samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
143 samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
148 samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
149 samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
[all …]
H A Dexynos5260-pinctrl.dtsi3 * Samsung's Exynos5260 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5260 SoC pin-mux and pin-config options are listed as device
201 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
202 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
203 samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>;
208 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
209 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
210 samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>;
215 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
216 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
[all …]
H A Dexynos5410-pinctrl.dtsi3 * Exynos5410 SoC pin-mux and pin-config device tree source
282 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
283 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
284 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
289 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
290 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
291 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
296 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
297 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
298 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
[all …]
/linux/arch/arm64/boot/dts/tesla/
H A Dfsd-pinctrl.dtsi56 samsung,pin-function = <FSD_PIN_FUNC_2>;
57 samsung,pin-pud = <FSD_PIN_PULL_DOWN>;
58 samsung,pin-drv = <FSD_PIN_DRV_LV4>;
63 samsung,pin-function = <FSD_PIN_FUNC_2>;
64 samsung,pin-pud = <FSD_PIN_PULL_UP>;
65 samsung,pin-drv = <FSD_PIN_DRV_LV4>;
70 samsung,pin-function = <FSD_PIN_FUNC_2>;
71 samsung,pin-pud = <FSD_PIN_PULL_DOWN>;
72 samsung,pin-drv = <FSD_PIN_DRV_LV6>;
77 samsung,pin-function = <FSD_PIN_FUNC_2>;
[all …]
/linux/drivers/pinctrl/renesas/
H A Dpinctrl-rza1.c3 * Combined GPIO and pin controller support for Renesas RZ/A1 (r7s72100) SoC
9 * This pin controller/gpio combined driver supports Renesas devices of RZ/A1
57 * Use 16 lower bits [15:0] for pin identifier
58 * Use 16 higher bits [31:16] for pin mux function
70 /* Pin mux flags */
80 * rza1_bidir_pin - describe a single pin that needs bidir flag applied.
83 u8 pin: 4; member
97 * rza1_swio_pin - describe a single pin that needs swio flag applied.
100 u16 pin: 4; member
127 { .pin = 0, .func = 1 },
[all …]
/linux/drivers/dpll/
H A Ddpll_core.c75 void dpll_pin_notify(struct dpll_pin *pin, u64 src_clock_id, in dpll_pin_notify() argument
79 .pin = pin, in dpll_pin_notify()
80 .id = pin->id, in dpll_pin_notify()
81 .idx = pin->pin_idx, in dpll_pin_notify()
82 .clock_id = pin->clock_id, in dpll_pin_notify()
83 .fwnode = pin->fwnode, in dpll_pin_notify()
84 .prop = &pin->prop, in dpll_pin_notify()
127 static void dpll_pin_tracker_alloc(struct dpll_pin *pin, dpll_tracker *tracker) in dpll_pin_tracker_alloc() argument
130 ref_tracker_alloc(&pin->refcnt_tracker, tracker, GFP_KERNEL); in dpll_pin_tracker_alloc()
134 static void dpll_pin_tracker_free(struct dpll_pin *pin, dpll_tracker *tracker) in dpll_pin_tracker_free() argument
[all …]
/linux/arch/arm64/boot/dts/actions/
H A Ds900-bubblegum-96.dts69 * NC = not connected (pin out but not routed from the chip to
71 * "[PER]" = pin is muxed for [peripheral] (not GPIO)
94 "GPIO-A", /* GPIO_0, LSEC pin 23 */
95 "GPIO-B", /* GPIO_1, LSEC pin 24 */
96 "GPIO-C", /* GPIO_2, LSEC pin 25 */
97 "GPIO-D", /* GPIO_3, LSEC pin 26 */
98 "GPIO-E", /* GPIO_4, LSEC pin 27 */
99 "GPIO-F", /* GPIO_5, LSEC pin 28 */
100 "GPIO-G", /* GPIO_6, LSEC pin 29 */
101 "GPIO-H", /* GPIO_7, LSEC pin 30 */
[all …]
/linux/drivers/net/ethernet/intel/ice/
H A Dice_dpll.c58 * enum ice_dpll_pin_type - enumerate ice pin types:
59 * @ICE_DPLL_PIN_INVALID: invalid pin type
60 * @ICE_DPLL_PIN_TYPE_INPUT: input pin
61 * @ICE_DPLL_PIN_TYPE_OUTPUT: output pin
62 * @ICE_DPLL_PIN_TYPE_RCLK_INPUT: recovery clock input pin
64 * @ICE_DPLL_PIN_TYPE_TXCLK: transmit clock reference input pin
93 * ice_dpll_is_sw_pin - check if given pin shall be controlled by SW
95 * @index: index of a pin as understood by FW
98 * Check if the pin shall be controlled by SW - instead of providing raw access
99 * for pin control. For E810 NIC with dpll there is additional MUX-related logic
[all …]
/linux/Documentation/netlink/specs/
H A Ddpll.yaml22 doc: highest prio input pin auto selected by dpll
79 locked on an input pin of type PIN_TYPE_SYNCE_ETH_PORT.
86 locked on an input pin of type PIN_TYPE_SYNCE_ETH_PORT.
147 name: pin-type
149 defines possible types of a pin, valid values for DPLL_A_PIN_TYPE
178 name: pin-direction
180 defines possible direction of a pin, valid values for
185 doc: pin used as a input of a signal
189 doc: pin used to output the signal
193 name: pin-frequency-1-hz
[all …]
/linux/drivers/dpll/zl3073x/
H A Ddpll.c30 * struct zl3073x_dpll_pin - DPLL pin
31 * @list: this DPLL pin list entry
32 * @dpll: DPLL the pin is registered to
37 * @dir: pin direction
38 * @id: pin id
39 * @prio: pin priority <0, 14>
43 * @phase_offset: last saved pin phase offset
73 * zl3073x_dpll_is_input_pin - check if the pin is input one
74 * @pin: pin to check
76 * Return: true if pin is input, false if pin is output.
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dpinmux-node.yaml7 title: Generic Pin Multiplexing Node
13 The contents of the pin configuration child nodes are defined by the binding
14 for the individual pin controller device. The pin configuration nodes need not
15 be direct children of the pin controller device; they may be grandchildren,
18 the binding for the individual pin controller device.
20 While not required to be used, there are 3 generic forms of pin muxing nodes
21 which pin controller devices can use.
23 pin multiplexing nodes:
45 pin controller hardware. For hardware where there is a large number of identical
46 pin controller instances, naming each pin and function can easily become
[all …]
/linux/drivers/gpio/
H A Dgpio-zynqmp-modepin.c3 * Driver for the ps-mode pin configuration.
22 * modepin_gpio_get_value - Get the state of the specified pin of GPIO device
24 * @pin: gpio pin number within the device
26 * This function reads the state of the specified pin of the GPIO device.
28 * Return: 0 if the pin is low, 1 if pin is high, -EINVAL wrong pin configured
31 static int modepin_gpio_get_value(struct gpio_chip *chip, unsigned int pin) in modepin_gpio_get_value() argument
43 if (regval & BIT(pin)) in modepin_gpio_get_value()
44 return !!(regval & BIT(pin + 8)); in modepin_gpio_get_value()
46 return !!(regval & BIT(pin + 4)); in modepin_gpio_get_value()
50 * modepin_gpio_set_value - Modify the state of the pin with specified value
[all …]

12345678910>>...114