Home
last modified time | relevance | path

Searched full:pads (Results 1 – 25 of 239) sorted by relevance

12345678910

/freebsd/sys/contrib/device-tree/src/arm64/nvidia/
H A Dtegra234-p3740-0002.dtsi77 pads {
168 phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>,
169 <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>;
176 phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>,
177 <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}>,
178 <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-2}>,
179 <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-3}>,
180 <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-0}>,
181 <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>,
182 <&{/bus@0/padctl@3520000/pads/usb
[all...]
H A Dtegra234-p3768-0000.dtsi45 pads {
120 phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>,
121 <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>;
128 phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>,
129 <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}>,
130 <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-2}>,
131 <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-0}>,
132 <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>;
H A Dtegra234-p3768-0000+p3767.dtsi63 pads {
138 phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>,
139 <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>;
146 phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>,
147 <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}>,
148 <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-2}>,
149 <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-0}>,
150 <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>;
H A Dtegra234-p3740-0002+p3701-0008.dts126 pads {
213 phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>,
214 <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>;
221 phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>,
222 <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}>,
223 <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-2}>,
224 <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-3}>,
225 <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-0}>,
226 <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>,
227 <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-2}>;
H A Dtegra234-p3737-0000+p3701-0000.dts124 pads {
228 phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>,
229 <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>;
236 phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>,
237 <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}>,
238 <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-2}>,
239 <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-3}>,
240 <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-0}>,
241 <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>,
242 <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-2}>;
/freebsd/sys/contrib/device-tree/Bindings/display/
H A Darm,pl11x.txt48 - arm,pl11x,tft-r0g0b0-pads: an array of three 32-bit values,
49 defining the way CLD pads are wired up; first value
58 arm,pl11x,tft-r0g0b0-pads = <4 15 20>;
60 arm,pl11x,tft-r0g0b0-pads = <1 7 13>;
62 arm,pl11x,tft-r0g0b0-pads = <3 11 19>;
64 arm,pl11x,tft-r0g0b0-pads = <3 10 19>;
66 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
68 arm,pl11x,tft-r0g0b0-pads = <16 8 0>;
H A Darm,pl11x.yaml94 arm,pl11x,tft-r0g0b0-pads:
103 CLD[23:0] pads are wired up.
111 arm,pl11x,tft-r0g0b0-pads = <4 15 20>;
113 arm,pl11x,tft-r0g0b0-pads = <1 7 13>;
115 arm,pl11x,tft-r0g0b0-pads = <3 11 19>;
117 arm,pl11x,tft-r0g0b0-pads = <3 10 19>;
119 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
121 arm,pl11x,tft-r0g0b0-pads = <16 8 0>;
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dnvidia,tegra20-usb-phy.yaml50 - description: UTMI pads control registers clock
56 - description: UTMI pads control registers clock
72 - const: utmi-pads
78 - const: utmi-pads
90 - description: UTMI pads reset
98 - const: utmi-pads
271 - const: utmi-pads
288 - const: utmi-pads
340 clock-names = "reg", "pll_u", "utmi-pads";
342 reset-names = "usb", "utmi-pads";
[all …]
H A Dnvidia,tegra124-xusb-padctl.txt5 signals) which connect directly to pins/pads on the SoC package. Each lane
20 Pads will be represented as children of the top-level XUSB pad controller
75 A required child node named "pads" contains a list of subnodes, one for each
76 of the pads exposed by the XUSB pad controller. Each pad may need additional
83 For Tegra124 and Tegra132, the following pads exist: usb2, ulpi, hsic, pcie
84 and sata. No extra resources are required for operation of these pads.
86 For Tegra210, the following pads exist: usb2, hsic, pcie and sata. Below is
280 pads {
412 pads {
508 pads {
[all …]
H A Dnvidia,tegra186-xusb-padctl.yaml15 signals) which connect directly to pins/pads on the SoC package. Each lane
30 Pads will be represented as children of the top-level XUSB pad controller
83 pads:
84 description: A required child node named "pads" contains a list of
85 subnodes, one for each of the pads exposed by the XUSB pad controller.
447 pads {
H A Dnvidia,tegra124-xusb-padctl.yaml15 signals) which connect directly to pins/pads on the SoC package. Each lane
30 Pads will be represented as children of the top-level XUSB pad controller
80 pads:
81 description: A required child node named "pads" contains a list of
82 subnodes, one for each of the pads exposed by the XUSB pad controller.
535 pads {
/freebsd/contrib/ncurses/man/
H A Dcurs_pad.3x54 create and display \fIcurses\fR pads
78 Pads can be used when a large window is needed,
80 Pads are not automatically refreshed by scrolling or input-echoing
83 Pads cannot be refreshed with \fB\%wrefresh\fP(3X);
121 except that they operate on pads rather than windows.
214 These graphical pads could be much larger than the computer's display.
272 that pads and windows are handled distinctly, and
275 pads versus windows consistently.
/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dnvidia,tegra20-pcie.txt17 "pads": PADS registers
171 reg = <0x80003000 0x00000800 /* PADS registers */
174 reg-names = "pads", "afi", "cs";
272 reg = <0x00003000 0x00000800 /* PADS registers */
275 reg-names = "pads", "afi", "cs";
377 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
380 reg-names = "pads", "afi", "cs";
452 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
459 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
473 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/ata/
H A Dcortina,gemini-sata-bridge.txt20 ata0 slave interface brought out on IDE pads
23 ata1 slave interface brought out on IDE pads
27 on IDE pads
31 on IDE pads
H A Dcortina,gemini-sata-bridge.yaml58 ata0 slave interface brought out on IDE pads
61 ata1 slave interface brought out on IDE pads
64 ata0 master and slave interfaces brought out on IDE pads
67 ata1 master and slave interfaces brought out on IDE pads
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dnvidia,tegra124-dpaux-padctl.txt21 needed to describe the pin mux'ing options for the DPAUX pads.
23 single set of pads, the child nodes only need to describe the pad group
24 the functions are being applied to rather than the individual pads.
H A Dfsl,imx7d-pinctrl.txt22 Peripherals using pads from iomuxc-lpsr support low state retention power
23 state, under LPSR mode GPIO's state of pads are retain.
57 advantages of LPSR power mode, is also possible that an IP to use pads from
H A Dnvidia,tegra124-xusb-padctl.txt11 assigned to one out of a set of different pads. Some of these pads have an
40 Each subnode describes groups of lanes along with parameters and pads that
/freebsd/sys/contrib/device-tree/Bindings/display/tegra/
H A Dnvidia,tegra124-dpaux.yaml84 DPAUX pads. Furthermore, given that the pad functions are only
85 applicable to a single set of pads, the child nodes only need
87 rather than the individual pads.
H A Dnvidia,tegra114-mipi.txt10 - #nvidia,mipi-calibrate-cells: Should be 1. The cell is a bitmask of the pads
14 phandle to refer to the calibration controller node and a bitmask of the pads
/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Dnvidia,tegra124-xusb.txt43 configure the USB pads used by the XHCI controller
119 phys = <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-1}>, /* mini-PCIe USB */
120 <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-2}>, /* USB A */
121 <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-0}>; /* USB A */
/freebsd/sys/contrib/device-tree/Bindings/arm/tegra/
H A Dnvidia,tegra186-pmc.yaml103 The following pads are present on Tegra186:
111 The following pads are present on Tegra194:
147 The power state can be configured on all of the above pads
148 except for ao-hv. Following pads have software configurable
H A Dnvidia,tegra20-pmc.yaml289 The following pads are present on Tegra124 and Tegra132
294 The following pads are present on Tegra210
321 pads. None of the Tegra124 or Tegra132 pads support signaling
323 All of the listed Tegra210 pads except pex-cntrl support power
325 on below Tegra210 pads.
H A Dnvidia,tegra186-pmc.txt57 The following pads are present on Tegra186:
81 Note: The power state can be configured on all of the above pads except
82 for ao-hv. Following pads have software configurable signaling
/freebsd/sys/contrib/device-tree/Bindings/soc/tegra/
H A Dnvidia,tegra20-pmc.yaml270 The following pads are present on Tegra124 and Tegra132:
277 The following pads are present on Tegra210:
306 Power state can be configured on all Tegra124 and Tegra132 pads.
307 None of the Tegra124 or Tegra132 pads support signaling voltage
308 switching. All of the listed Tegra210 pads except pex-cntrl support
310 on the following Tegra210 pads:

12345678910