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/linux/arch/m68k/include/asm/
H A Dmcf_pgtable.h10 * after masking from the pte.
99 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) in pte_modify() argument
101 pte_val(pte) = (pte_val(pte) & CF_PAGE_CHG_MASK) | pgprot_val(newprot); in pte_modify()
102 return pte; in pte_modify()
112 #define __pte_page(pte) ((void *) (pte_val(pte) & PAGE_MASK)) argument
115 static inline int pte_none(pte_t pte) in pte_none() argument
117 return !pte_val(pte); in pte_none()
120 static inline int pte_present(pte_t pte) in pte_present() argument
122 return pte_val(pte) & CF_PAGE_VALID; in pte_present()
131 #define pte_page(pte) virt_to_page(__pte_page(pte)) argument
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H A Dsun3_pgtable.h29 /* Page protection values within PTE. */
79 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) in pte_modify() argument
81 pte_val(pte) = (pte_val(pte) & SUN3_PAGE_CHG_MASK) | pgprot_val(newprot); in pte_modify()
82 return pte; in pte_modify()
87 #define __pte_page(pte) \ argument
88 (__va ((pte_val (pte) & SUN3_PAGE_PGNUM_MASK) << PAGE_SHIFT))
95 static inline int pte_none (pte_t pte) { return !pte_val (pte); } in pte_none() argument
96 static inline int pte_present (pte_t pte) { return pte_val (pte) & SUN3_PAGE_VALID; } in pte_present() argument
103 #define pte_pfn(pte) (pte_val(pte) & SUN3_PAGE_PGNUM_MASK) argument
107 #define pte_page(pte) virt_to_page(__pte_page(pte)) argument
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H A Dmotorola_pgtable.h84 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) in pte_modify() argument
86 pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); in pte_modify()
87 return pte; in pte_modify()
100 #define __pte_page(pte) ((unsigned long)__va(pte_val(pte) & PAGE_MASK)) argument
105 #define pte_none(pte) (!pte_val(pte)) argument
106 #define pte_present(pte) (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PROTNONE)) argument
110 #define pte_page(pte) virt_to_page(__va(pte_val(pte))) argument
111 #define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT) argument
135 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
146 static inline int pte_write(pte_t pte) { return !(pte_val(pte) & _PAGE_RONLY); } in pte_write() argument
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/linux/arch/powerpc/include/asm/nohash/
H A Dpgtable.h37 static inline unsigned long pte_huge_size(pte_t pte) in pte_huge_size() argument
44 * PTE updates. This function is called whenever an existing
45 * valid PTE is updated. This does -not- include set_pte_at()
46 * which nowadays only sets a new PTE.
49 * and the PTE may be either 32 or 64 bit wide. In the later case,
50 * when using atomic updates, only the low part of the PTE is
140 /* Set the dirty and/or accessed bits atomically in a linux PTE */
157 /* Generic accessors to PTE bits */
159 static inline pte_t pte_mkwrite_novma(pte_t pte) in pte_mkwrite_novma() argument
164 return __pte(pte_val(pte) | _PAGE_RW); in pte_mkwrite_novma()
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/linux/arch/arm64/include/asm/
H A Dpgtable.h46 * These barriers are emitted under certain conditions after a pte entry in emit_pte_barriers()
51 * setting the pte to valid won't cause a spurious fault. If the thread in emit_pte_barriers()
111 pr_err("%s:%d: bad pte %016llx.\n", __FILE__, __LINE__, pte_val(e))
114 static inline phys_addr_t __pte_to_phys(pte_t pte) in __pte_to_phys() argument
116 pte_val(pte) &= ~PTE_MAYBE_SHARED; in __pte_to_phys()
117 return (pte_val(pte) & PTE_ADDR_LOW) | in __pte_to_phys()
118 ((pte_val(pte) & PTE_ADDR_HIGH) << PTE_ADDR_HIGH_SHIFT); in __pte_to_phys()
125 static inline phys_addr_t __pte_to_phys(pte_t pte) in __pte_to_phys() argument
127 return pte_val(pte) & PTE_ADDR_LOW; in __pte_to_phys()
136 #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT) argument
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/linux/arch/powerpc/include/asm/book3s/32/
H A Dpgtable.h21 #define _PAGE_PRESENT 0x001 /* software: pte contains a translation */
22 #define _PAGE_HASHPTE 0x002 /* hash_page has made an HPTE for this pte */
35 /* We never clear the high word of the pte */
53 * Location of the PFN in the PTE. Most 32-bit platforms use the same
111 /* Bits to mask out from a PMD to get to the PTE page */
120 * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus
125 * level has 2048 entries and the second level has 512 64-bit PTE entries.
209 * Bits in a linux-style PTE. These match the bits in the
210 * (hardware-defined) PowerPC PTE as closely as possible.
247 * PTE updates. This function is called whenever an existing
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/linux/include/asm-generic/
H A Dhugetlb.h8 static inline unsigned long huge_pte_write(pte_t pte) in huge_pte_write() argument
10 return pte_write(pte); in huge_pte_write()
13 static inline unsigned long huge_pte_dirty(pte_t pte) in huge_pte_dirty() argument
15 return pte_dirty(pte); in huge_pte_dirty()
18 static inline pte_t huge_pte_mkwrite(pte_t pte) in huge_pte_mkwrite() argument
20 return pte_mkwrite_novma(pte); in huge_pte_mkwrite()
24 static inline pte_t huge_pte_wrprotect(pte_t pte) in huge_pte_wrprotect() argument
26 return pte_wrprotect(pte); in huge_pte_wrprotect()
30 static inline pte_t huge_pte_mkdirty(pte_t pte) in huge_pte_mkdirty() argument
32 return pte_mkdirty(pte); in huge_pte_mkdirty()
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/linux/arch/parisc/include/asm/
H A Dpgtable.h64 extern void __update_cache(pte_t pte);
79 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
104 * done to get usable bits out of the PTE) */
182 /* this defines the shift to the usable bits in the PTE it is set so
187 /* PFN_PTE_SHIFT defines the shift of a PTE value to access the PFN field */
304 static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; } in pte_dirty() argument
305 static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } in pte_young() argument
306 static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; } in pte_write() argument
307 static inline int pte_special(pte_t pte) { return pte_val(pte) & _PAGE_SPECIAL; } in pte_special() argument
309 static inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~_PAGE_DIRTY; return pte; } in pte_mkclean() argument
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/linux/arch/x86/include/asm/
H A Dpgtable.h60 #define set_pte(ptep, pte) native_set_pte(ptep, pte) argument
62 #define set_pte_atomic(ptep, pte) \ argument
63 native_set_pte_atomic(ptep, pte)
148 static inline bool pte_dirty(pte_t pte) in pte_dirty() argument
150 return pte_flags(pte) & _PAGE_DIRTY_BITS; in pte_dirty()
153 static inline bool pte_shstk(pte_t pte) in pte_shstk() argument
156 (pte_flags(pte) & (_PAGE_RW | _PAGE_DIRTY)) == _PAGE_DIRTY; in pte_shstk()
159 static inline int pte_young(pte_t pte) in pte_young() argument
161 return pte_flags(pte) & _PAGE_ACCESSED; in pte_young()
164 static inline bool pte_decrypted(pte_t pte) in pte_decrypted() argument
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/linux/arch/riscv/include/asm/
H A Dpgtable.h281 static inline unsigned long pte_napot(pte_t pte) in pte_napot() argument
283 return pte_val(pte) & _PAGE_NAPOT; in pte_napot()
286 static inline pte_t pte_mknapot(pte_t pte, unsigned int order) in pte_mknapot() argument
292 return __pte((pte_val(pte) & napot_mask) | napot_bit | _PAGE_NAPOT); in pte_mknapot()
299 static inline unsigned long pte_napot(pte_t pte) in pte_napot() argument
307 static inline unsigned long pte_pfn(pte_t pte) in pte_pfn() argument
309 unsigned long res = __page_val_to_pfn(pte_val(pte)); in pte_pfn()
311 if (has_svnapot() && pte_napot(pte)) in pte_pfn()
330 static inline pgprot_t pte_pgprot(pte_t pte) in pte_pgprot() argument
332 unsigned long pfn = pte_pfn(pte); in pte_pgprot()
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/linux/arch/loongarch/include/asm/
H A Dpgtable.h132 pr_err("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
280 #define pte_pfn(x) ((unsigned long)(((x).pte & _PFN_MASK) >> PFN_PTE_SHIFT))
329 pte_t pte; in mk_swap_pte() local
330 pte_val(pte) = ((type & __SWP_TYPE_MASK) << __SWP_TYPE_SHIFT) | (offset << __SWP_OFFSET_SHIFT); in mk_swap_pte()
331 return pte; in mk_swap_pte()
340 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) argument
343 static inline bool pte_swp_exclusive(pte_t pte) in pte_swp_exclusive() argument
345 return pte_val(pte) & _PAGE_SWP_EXCLUSIVE; in pte_swp_exclusive()
348 static inline pte_t pte_swp_mkexclusive(pte_t pte) in pte_swp_mkexclusive() argument
350 pte_val(pte) |= _PAGE_SWP_EXCLUSIVE; in pte_swp_mkexclusive()
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/linux/drivers/iommu/
H A Dio-pgtable-dart.c63 /* marks PTE as valid */
67 #define iopte_deref(pte, d) __va(iopte_to_paddr(pte, d)) argument
85 dart_iopte pte; in paddr_to_iopte() local
91 pte = paddr >> APPLE_DART2_PADDR_SHIFT; in paddr_to_iopte()
92 pte &= APPLE_DART2_PADDR_MASK; in paddr_to_iopte()
94 return pte; in paddr_to_iopte()
97 static phys_addr_t iopte_to_paddr(dart_iopte pte, in iopte_to_paddr() argument
103 return pte & APPLE_DART1_PADDR_MASK; in iopte_to_paddr()
106 paddr = pte & APPLE_DART2_PADDR_MASK; in iopte_to_paddr()
118 dart_iopte pte = prot; in dart_init_pte() local
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H A Dio-pgtable-arm-v7s.c78 /* PTE type bits: these are all mixed up with XN/PXN bits in most cases */
83 #define ARM_V7S_PTE_IS_VALID(pte) (((pte) & 0x3) != 0) argument
84 #define ARM_V7S_PTE_IS_TABLE(pte, lvl) \ argument
85 ((lvl) == 1 && (((pte) & 0x3) == ARM_V7S_PTE_TYPE_TABLE))
99 * a level 1 PTE vs. bits [11:4] at level 2. Thus we define the individual
100 * fields relative to that 8-bit block, plus a total shift relative to the PTE.
171 static bool arm_v7s_pte_is_cont(arm_v7s_iopte pte, int lvl);
184 static arm_v7s_iopte to_mtk_iopte(phys_addr_t paddr, arm_v7s_iopte pte) in to_mtk_iopte() argument
187 pte |= ARM_V7S_ATTR_MTK_PA_BIT32; in to_mtk_iopte()
189 pte |= ARM_V7S_ATTR_MTK_PA_BIT33; in to_mtk_iopte()
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/linux/arch/powerpc/include/asm/book3s/64/
H A Dpgtable.h42 #define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */
44 * We need to mark a pmd pte invalid while splitting. We can do that by clearing
45 * the _PAGE_PRESENT bit. But then that will be taken as a swap pte. In order to
48 * We do that temporary invalidate for regular pte entry in ptep_set_access_flags
93 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE
95 * maps CI pte mapping.
99 * We support _RPAGE_PA_MAX bit real address in pte. On the linux side
165 * Because of use of pte fragments and THP, size of page table
222 /* Bits to mask out from a PMD to get to the PTE page */
391 static inline int pte_write(pte_t pte) in pte_write() argument
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/linux/arch/powerpc/kvm/
H A Dtrace_pr.h64 TP_PROTO(struct hpte_cache *pte),
65 TP_ARGS(pte),
77 __entry->host_vpn = pte->host_vpn;
78 __entry->pfn = pte->pfn;
79 __entry->eaddr = pte->pte.eaddr;
80 __entry->vpage = pte->pte.vpage;
81 __entry->raddr = pte->pte.raddr;
82 __entry->flags = (pte->pte.may_read ? 0x4 : 0) |
83 (pte->pte.may_write ? 0x2 : 0) |
84 (pte->pte.may_execute ? 0x1 : 0);
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H A Dbook3s_32_mmu.c70 struct kvmppc_pte *pte, bool data,
84 struct kvmppc_pte pte; in kvmppc_mmu_book3s_32_ea_to_vp() local
86 if (!kvmppc_mmu_book3s_32_xlate_bat(vcpu, eaddr, &pte, data, false)) in kvmppc_mmu_book3s_32_ea_to_vp()
87 return pte.vpage; in kvmppc_mmu_book3s_32_ea_to_vp()
128 struct kvmppc_pte *pte, bool data, in kvmppc_mmu_book3s_32_xlate_bat() argument
160 pte->vpage = (((u64)eaddr >> 12) & 0xffff) | vsid; in kvmppc_mmu_book3s_32_xlate_bat()
162 pte->raddr = bat->brpn | (eaddr & ~bat->bepi_mask); in kvmppc_mmu_book3s_32_xlate_bat()
163 pte->may_read = bat->pp; in kvmppc_mmu_book3s_32_xlate_bat()
164 pte->may_write = bat->pp > 1; in kvmppc_mmu_book3s_32_xlate_bat()
165 pte->may_execute = true; in kvmppc_mmu_book3s_32_xlate_bat()
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H A Dbook3s_pr_papr.c92 unsigned long pte[2]; in kvmppc_h_pr_remove() local
98 if (copy_from_user(pte, (void __user *)pteg, sizeof(pte))) in kvmppc_h_pr_remove()
100 pte[0] = be64_to_cpu((__force __be64)pte[0]); in kvmppc_h_pr_remove()
101 pte[1] = be64_to_cpu((__force __be64)pte[1]); in kvmppc_h_pr_remove()
104 if ((pte[0] & HPTE_V_VALID) == 0 || in kvmppc_h_pr_remove()
105 ((flags & H_AVPN) && (pte[0] & ~0x7fUL) != avpn) || in kvmppc_h_pr_remove()
106 ((flags & H_ANDCOND) && (pte[0] & avpn) != 0)) in kvmppc_h_pr_remove()
113 rb = compute_tlbie_rb(pte[0], pte[1], pte_index); in kvmppc_h_pr_remove()
117 kvmppc_set_gpr(vcpu, 4, pte[0]); in kvmppc_h_pr_remove()
118 kvmppc_set_gpr(vcpu, 5, pte[1]); in kvmppc_h_pr_remove()
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H A Dbook3s_64_mmu_radix.c22 #include <asm/pte-walk.h>
149 u64 pte, base, gpa; in kvmppc_mmu_walk_radix_tree() local
187 pte = __be64_to_cpu(rpte); in kvmppc_mmu_walk_radix_tree()
188 if (!(pte & _PAGE_PRESENT)) in kvmppc_mmu_walk_radix_tree()
191 if (pte & _PAGE_PTE) in kvmppc_mmu_walk_radix_tree()
194 base = pte & RPDB_MASK; in kvmppc_mmu_walk_radix_tree()
195 bits = pte & RPDS_MASK; in kvmppc_mmu_walk_radix_tree()
202 /* We found a valid leaf PTE */ in kvmppc_mmu_walk_radix_tree()
204 gpa = pte & 0x01fffffffffff000ul; in kvmppc_mmu_walk_radix_tree()
218 gpte->may_read = !!(pte & _PAGE_READ); in kvmppc_mmu_walk_radix_tree()
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/linux/arch/parisc/kernel/
H A Dentry.S380 /* Look up a PTE in a 2-Level scheme (faulting at each
386 .macro L2_ptep pmd,pte,index,va,fault
394 copy %r0,\pte
402 shladd \index,BITS_PER_PTE_ENTRY,\pmd,\pmd /* pmd is now pte */
405 /* Look up PTE in a 3-Level scheme. */
406 .macro L3_ptep pgd,pte,index,va,fault
408 copy %r0,\pte
414 L2_ptep \pgd,\pte,\index,\va,\fault
418 .macro ptl_lock spc,ptp,pte,tmp,tmp1,fault
425 LDREG 0(\ptp),\pte
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/linux/arch/s390/include/asm/
H A Dpgtable.h72 pr_err("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
187 #define _PAGE_LARGE 0x800 /* Bit to mark a large pte */
190 #define _PAGE_PRESENT 0x001 /* SW pte present bit */
191 #define _PAGE_YOUNG 0x004 /* SW pte young bit */
192 #define _PAGE_DIRTY 0x008 /* SW pte dirty bit */
193 #define _PAGE_READ 0x010 /* SW pte read bit */
194 #define _PAGE_WRITE 0x020 /* SW pte write bit */
199 #define _PAGE_SOFT_DIRTY 0x002 /* SW pte soft dirty bit */
206 #define _PAGE_SWP_EXCLUSIVE _PAGE_LARGE /* SW pte exclusive swap bit */
219 * handle_pte_fault uses pte_present and pte_none to find out the pte type
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/linux/arch/arm/include/asm/
H A Dpgalloc.h41 #define pud_populate(mm,pmd,pte) do { } while (0) argument
43 #define pud_populate(mm,pmd,pte) BUG() argument
50 static inline void clean_pte_table(pte_t *pte) in clean_pte_table() argument
52 clean_dcache_area(pte + PTE_HWTABLE_PTRS, PTE_HWTABLE_SIZE); in clean_pte_table()
56 * Allocate one PTE table.
58 * This actually allocates two hardware PTE tables, but we wrap this up
80 pte_t *pte = __pte_alloc_one_kernel(mm); in pte_alloc_one_kernel() local
82 if (pte) in pte_alloc_one_kernel()
83 clean_pte_table(pte); in pte_alloc_one_kernel()
85 return pte; in pte_alloc_one_kernel()
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/linux/arch/arm64/mm/
H A Dcontpte.c70 pte_t *ptep, pte_t pte) in contpte_convert() argument
79 pte = pfn_pte(ALIGN_DOWN(pte_pfn(pte), CONT_PTES), pte_pgprot(pte)); in contpte_convert()
85 pte = pte_mkdirty(pte); in contpte_convert()
88 pte = pte_mkyoung(pte); in contpte_convert()
179 * non-contiguous pte TLB entries to be flushed, leaving only the in contpte_convert()
231 __set_ptes(mm, start_addr, start_ptep, pte, CONT_PTES); in contpte_convert()
235 pte_t *ptep, pte_t pte) in __contpte_try_fold() argument
246 * their respective bits in the constituent pte entries. In order to in __contpte_try_fold()
250 * that the pte is not special - we never try to fold special mappings. in __contpte_try_fold()
269 page = pte_page(pte); in __contpte_try_fold()
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/linux/arch/x86/kernel/
H A Dhead32.c42 *pl2p = (pte_t){ .pte = 0 }; in zap_early_initrd_mapping()
45 *(pl2p + ((PAGE_OFFSET >> PGDIR_SHIFT))) = (pte_t) {.pte = 0}; in zap_early_initrd_mapping()
92 * to the first kernel PMD. Note the upper half of each PMD or PTE are
105 static __init __no_stack_protector pte_t init_map(pte_t pte, pte_t **ptep, pl2_t **pl2p, in init_map() argument
108 while ((pte.pte & PTE_PFN_MASK) < limit) { in init_map()
119 **ptep = pte; in init_map()
120 pte.pte += PAGE_SIZE; in init_map()
125 return pte; in init_map()
132 pte_t pte, *ptep = (pte_t *)__pa_nodebug(__brk_base); in mk_early_pgtbl_32() local
137 pte.pte = PTE_IDENT_ATTR; in mk_early_pgtbl_32()
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/linux/arch/powerpc/mm/book3s32/
H A Dhash_low.S31 #define PTE_FLAGS_OFFSET 4 /* offset of PTE flags, in bytes */
38 * Load a PTE into the hash table, if possible.
46 * mapping for the address. Otherwise it places an appropriate PTE
67 /* Get PTE (linux-style) and check access */
85 rlwinm. r8,r8,0,0,19 /* extract address of pte page */
103 rlwimi r8,r4,23,20,28 /* compute pte address */
112 * Update the linux PTE atomically. We do the lwarx up-front
115 * to update the PTE to set _PAGE_HASHPTE. -- paulus.
118 lwarx r6,0,r8 /* get linux-style pte, flag word */
141 lwzx r10,r6,r10 /* Get upper PTE word */
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/linux/arch/arc/include/asm/
H A Dpgtable-bits-arcv2.h27 #define _PAGE_PRESENT (1 << 9) /* PTE/TLB Valid (H) */
60 * Mapping of vm_flags (Generic VM) to PTE flags (arch specific)
80 #define pte_write(pte) (pte_val(pte) & _PAGE_WRITE) argument
81 #define pte_dirty(pte) (pte_val(pte) & _PAGE_DIRTY) argument
82 #define pte_young(pte) (pte_val(pte) & _PAGE_ACCESSED) argument
83 #define pte_special(pte) (pte_val(pte) & _PAGE_SPECIAL) argument
86 static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; }
98 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) in pte_modify() argument
100 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)); in pte_modify()
126 /* Decode a PTE containing swap "identifier "into constituents */
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