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/linux/arch/m68k/include/asm/
H A Dmcf_pgtable.h10 * after masking from the pte.
99 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) in pte_modify() argument
101 pte_val(pte) = (pte_val(pte) & CF_PAGE_CHG_MASK) | pgprot_val(newprot); in pte_modify()
102 return pte; in pte_modify()
112 #define __pte_page(pte) ((void *) (pte_val(pte) & PAGE_MASK)) argument
115 static inline int pte_none(pte_t pte) in pte_none() argument
117 return !pte_val(pte); in pte_none()
120 static inline int pte_present(pte_t pte) in pte_present() argument
122 return pte_val(pte) & CF_PAGE_VALID; in pte_present()
131 #define pte_page(pte) virt_to_page(__pte_page(pte)) argument
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H A Dsun3_pgtable.h29 /* Page protection values within PTE. */
79 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) in pte_modify() argument
81 pte_val(pte) = (pte_val(pte) & SUN3_PAGE_CHG_MASK) | pgprot_val(newprot); in pte_modify()
82 return pte; in pte_modify()
87 #define __pte_page(pte) \ argument
88 (__va ((pte_val (pte) & SUN3_PAGE_PGNUM_MASK) << PAGE_SHIFT))
95 static inline int pte_none (pte_t pte) { return !pte_val (pte); } in pte_none() argument
96 static inline int pte_present (pte_t pte) { return pte_val (pte) & SUN3_PAGE_VALID; } in pte_present() argument
103 #define pte_pfn(pte) (pte_val(pte) & SUN3_PAGE_PGNUM_MASK) argument
107 #define pte_page(pte) virt_to_page(__pte_page(pte)) argument
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H A Dmotorola_pgtable.h84 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) in pte_modify() argument
86 pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); in pte_modify()
87 return pte; in pte_modify()
100 #define __pte_page(pte) ((unsigned long)__va(pte_val(pte) & PAGE_MASK)) argument
105 #define pte_none(pte) (!pte_val(pte)) argument
106 #define pte_present(pte) (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PROTNONE)) argument
110 #define pte_page(pte) virt_to_page(__va(pte_val(pte))) argument
111 #define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT) argument
135 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
146 static inline int pte_write(pte_t pte) { return !(pte_val(pte) & _PAGE_RONLY); } in pte_write() argument
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/linux/arch/hexagon/include/asm/
H A Dpgtable.h21 * The PTE model described here is that of the Hexagon Virtual Machine,
30 * To maximize the comfort level for the PTE manipulation macros,
39 * We have a total of 4 "soft" bits available in the abstract PTE.
43 * the PTE describes MMU programming or swap space.
99 /* Any bigger and the PTE disappears. */
136 #define pte_mkhuge(pte) __pte((pte_val(pte) & ~0x3) | HVM_HUGEPAGE_SIZE) argument
143 extern void sync_icache_dcache(pte_t pte);
145 #define pte_present_exec_user(pte) \ argument
146 ((pte_val(pte) & (_PAGE_EXECUTE | _PAGE_USER)) == \
160 * L1 PTE (PMD/PGD) has 7 in the least significant bits. For the L2 PTE
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/linux/arch/arm64/include/asm/
H A Dpgtable.h46 * These barriers are emitted under certain conditions after a pte entry in emit_pte_barriers()
51 * setting the pte to valid won't cause a spurious fault. If the thread in emit_pte_barriers()
117 pr_err("%s:%d: bad pte %016llx.\n", __FILE__, __LINE__, pte_val(e))
120 static inline phys_addr_t __pte_to_phys(pte_t pte) in __pte_to_phys() argument
122 pte_val(pte) &= ~PTE_MAYBE_SHARED; in __pte_to_phys()
123 return (pte_val(pte) & PTE_ADDR_LOW) | in __pte_to_phys()
124 ((pte_val(pte) & PTE_ADDR_HIGH) << PTE_ADDR_HIGH_SHIFT); in __pte_to_phys()
131 static inline phys_addr_t __pte_to_phys(pte_t pte) in __pte_to_phys() argument
133 return pte_val(pte) & PTE_ADDR_LOW; in __pte_to_phys()
142 #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT) argument
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/linux/arch/csky/include/asm/
H A Dpgtable.h27 pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, (e).pte_low)
36 #define pte_none(pte) (!(pte_val(pte) & ~_PAGE_GLOBAL)) argument
37 #define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT) argument
42 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) argument
85 static inline void set_pte(pte_t *p, pte_t pte) in set_pte() argument
87 *p = pte; in set_pte()
141 static inline int pte_read(pte_t pte) in pte_read() argument
143 return pte.pte_low & _PAGE_READ; in pte_read()
146 static inline int pte_write(pte_t pte) in pte_write() argument
148 return (pte).pte_low & _PAGE_WRITE; in pte_write()
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/linux/arch/um/include/asm/
H A Dpgtable.h113 static inline int pte_none(pte_t pte) in pte_none() argument
115 return pte_is_zero(pte); in pte_none()
122 static inline int pte_read(pte_t pte) in pte_read() argument
124 return((pte_get_bits(pte, _PAGE_USER)) && in pte_read()
125 !(pte_get_bits(pte, _PAGE_PROTNONE))); in pte_read()
128 static inline int pte_exec(pte_t pte){ in pte_exec() argument
129 return((pte_get_bits(pte, _PAGE_USER)) && in pte_exec()
130 !(pte_get_bits(pte, _PAGE_PROTNONE))); in pte_exec()
133 static inline int pte_write(pte_t pte) in pte_write() argument
135 return((pte_get_bits(pte, _PAGE_RW)) && in pte_write()
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/linux/arch/openrisc/include/asm/
H A Dpgtable.h44 /* Certain architectures need to do special things when pte's
102 * An OR32 PTE looks like this:
117 * PTE as per above
120 #define _PAGE_CC 0x001 /* software: pte contains a translation */
200 static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_READ; } in pte_read() argument
201 static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; } in pte_write() argument
202 static inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_EXEC; } in pte_exec() argument
203 static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; } in pte_dirty() argument
204 static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } in pte_young() argument
206 static inline pte_t pte_wrprotect(pte_t pte) in pte_wrprotect() argument
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/linux/arch/microblaze/include/asm/
H A Dpgtable.h84 * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus
107 printk(KERN_ERR "%s:%d: bad pte "PTE_FMT".\n", \
114 * Bits in a linux-style PTE. These match the bits in the
115 * (hardware-defined) PTE as closely as possible.
124 * Where possible we make the Linux PTE bits match up with this
137 * - All other bits of the PTE are loaded into TLBLO without
139 * software PTE bits. We actually use bits 21, 24, 25, and
146 #define _PAGE_PRESENT 0x002 /* software: PTE contains a translation */
180 * PTE if CONFIG_SMP is defined (hash_page does this); there is no need
181 * to have it in the Linux PTE, and in fact the bit could be reused for
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/linux/arch/nios2/include/asm/
H A Dpgtable.h87 static inline int pte_write(pte_t pte) \ in pte_write() argument
88 { return pte_val(pte) & _PAGE_WRITE; } in pte_write()
89 static inline int pte_dirty(pte_t pte) \ in pte_dirty() argument
90 { return pte_val(pte) & _PAGE_DIRTY; } in pte_dirty()
91 static inline int pte_young(pte_t pte) \ in pte_young() argument
92 { return pte_val(pte) & _PAGE_ACCESSED; } in pte_young()
105 static inline int pte_none(pte_t pte) in pte_none() argument
107 return !(pte_val(pte) & ~(_PAGE_GLOBAL|0xf)); in pte_none()
110 static inline int pte_present(pte_t pte) \ in pte_present() argument
111 { return pte_val(pte) & _PAGE_PRESENT; } in pte_present()
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/linux/arch/sparc/include/asm/
H A Dpgtable_64.h111 /* PTE bits which are the same in SUN4U and SUN4V format. */
118 /* SUN4U pte bits... */
149 /* SUN4V pte bits... */
232 pte_t pte = pfn_pte(page_nr, pgprot); in pfn_pmd() local
234 return __pmd(pte_val(pte)); in pfn_pmd()
239 static inline unsigned long pte_pfn(pte_t pte) in pte_pfn() argument
252 : "r" (pte_val(pte)), in pte_pfn()
260 static inline pte_t pte_modify(pte_t pte, pgprot_t prot) in pte_modify() argument
315 return __pte((pte_val(pte) & mask) | (pgprot_val(prot) & ~mask)); in pte_modify()
321 pte_t pte = __pte(pmd_val(pmd)); in pmd_modify() local
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H A Dpgtable_32.h94 /* Certain architectures need to do special things when pte's
148 static inline int pte_present(pte_t pte) in pte_present() argument
150 return ((pte_val(pte) & SRMMU_ET_MASK) == SRMMU_ET_PTE); in pte_present()
153 static inline int pte_none(pte_t pte) in pte_none() argument
155 return !pte_val(pte); in pte_none()
212 static inline int pte_write(pte_t pte) in pte_write() argument
214 return pte_val(pte) & SRMMU_WRITE; in pte_write()
217 static inline int pte_dirty(pte_t pte) in pte_dirty() argument
219 return pte_val(pte) & SRMMU_DIRTY; in pte_dirty()
222 static inline int pte_young(pte_t pte) in pte_young() argument
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/linux/drivers/iommu/intel/
H A Dpasid.c244 struct pasid_entry *pte; in intel_pasid_tear_down_entry() local
248 pte = intel_pasid_get_entry(dev, pasid); in intel_pasid_tear_down_entry()
249 if (WARN_ON(!pte)) { in intel_pasid_tear_down_entry()
254 if (!pasid_pte_is_present(pte)) { in intel_pasid_tear_down_entry()
255 if (!pasid_pte_is_fault_disabled(pte)) { in intel_pasid_tear_down_entry()
256 WARN_ON(READ_ONCE(pte->val[0]) != 0); in intel_pasid_tear_down_entry()
267 pasid_clear_entry(pte); in intel_pasid_tear_down_entry()
274 did = pasid_get_domain_id(pte); in intel_pasid_tear_down_entry()
275 pgtt = pasid_pte_get_pgtt(pte); in intel_pasid_tear_down_entry()
276 pasid_clear_present(pte); in intel_pasid_tear_down_entry()
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/linux/include/asm-generic/
H A Dhugetlb.h8 static inline unsigned long huge_pte_write(pte_t pte) in huge_pte_write() argument
10 return pte_write(pte); in huge_pte_write()
13 static inline unsigned long huge_pte_dirty(pte_t pte) in huge_pte_dirty() argument
15 return pte_dirty(pte); in huge_pte_dirty()
18 static inline pte_t huge_pte_mkwrite(pte_t pte) in huge_pte_mkwrite() argument
20 return pte_mkwrite_novma(pte); in huge_pte_mkwrite()
24 static inline pte_t huge_pte_wrprotect(pte_t pte) in huge_pte_wrprotect() argument
26 return pte_wrprotect(pte); in huge_pte_wrprotect()
30 static inline pte_t huge_pte_mkdirty(pte_t pte) in huge_pte_mkdirty() argument
32 return pte_mkdirty(pte); in huge_pte_mkdirty()
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/linux/arch/parisc/include/asm/
H A Dpgtable.h64 extern void __update_cache(pte_t pte);
79 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
104 * done to get usable bits out of the PTE) */
182 /* this defines the shift to the usable bits in the PTE it is set so
187 /* PFN_PTE_SHIFT defines the shift of a PTE value to access the PFN field */
315 static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; } in pte_dirty() argument
316 static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } in pte_young() argument
317 static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; } in pte_write() argument
318 static inline int pte_special(pte_t pte) { return pte_val(pte) & _PAGE_SPECIAL; } in pte_special() argument
320 static inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~_PAGE_DIRTY; return pte; } in pte_mkclean() argument
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/linux/arch/xtensa/include/asm/
H A Dpgtable.h32 * One page (4 kB) of 1024 (PTRS_PER_PGD) pointers to PTE tables
42 * PTE tables (page table entry), ie. 1st-level page tables:
43 * One page (4 kB) of 1024 (PTRS_PER_PTE) PTEs with a special PTE
85 * For the Xtensa architecture, the PTE layout is as follows:
144 /* We use invalid attribute values to distinguish special pte entries */
208 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
225 * The pmd contains the kernel virtual address of the pte page.
232 * pte status.
234 # define pte_none(pte) (pte_val(pte) == (_PAGE_CA_INVALID | _PAGE_USER)) argument
236 # define pte_present(pte) ((pte_val(pte) & _PAGE_CA_MASK) != _PAGE_CA_INVALID) argument
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/linux/arch/riscv/include/asm/
H A Dpgtable.h296 static inline unsigned long pte_napot(pte_t pte) in pte_napot() argument
298 return pte_val(pte) & _PAGE_NAPOT; in pte_napot()
301 static inline pte_t pte_mknapot(pte_t pte, unsigned int order) in pte_mknapot() argument
307 return __pte((pte_val(pte) & napot_mask) | napot_bit | _PAGE_NAPOT); in pte_mknapot()
314 static inline unsigned long pte_napot(pte_t pte) in pte_napot() argument
322 static inline unsigned long pte_pfn(pte_t pte) in pte_pfn() argument
324 unsigned long res = __page_val_to_pfn(pte_val(pte)); in pte_pfn()
326 if (has_svnapot() && pte_napot(pte)) in pte_pfn()
345 static inline pgprot_t pte_pgprot(pte_t pte) in pte_pgprot() argument
347 unsigned long pfn = pte_pfn(pte); in pte_pgprot()
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/linux/drivers/iommu/
H A Dio-pgtable-dart.c63 /* marks PTE as valid */
67 #define iopte_deref(pte, d) __va(iopte_to_paddr(pte, d)) argument
85 dart_iopte pte; in paddr_to_iopte() local
91 pte = paddr >> APPLE_DART2_PADDR_SHIFT; in paddr_to_iopte()
92 pte &= APPLE_DART2_PADDR_MASK; in paddr_to_iopte()
94 return pte; in paddr_to_iopte()
97 static phys_addr_t iopte_to_paddr(dart_iopte pte, in iopte_to_paddr() argument
103 return pte & APPLE_DART1_PADDR_MASK; in iopte_to_paddr()
106 paddr = pte & APPLE_DART2_PADDR_MASK; in iopte_to_paddr()
118 dart_iopte pte = prot; in dart_init_pte() local
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H A Dio-pgtable-arm-v7s.c78 /* PTE type bits: these are all mixed up with XN/PXN bits in most cases */
83 #define ARM_V7S_PTE_IS_VALID(pte) (((pte) & 0x3) != 0) argument
84 #define ARM_V7S_PTE_IS_TABLE(pte, lvl) \ argument
85 ((lvl) == 1 && (((pte) & 0x3) == ARM_V7S_PTE_TYPE_TABLE))
99 * a level 1 PTE vs. bits [11:4] at level 2. Thus we define the individual
100 * fields relative to that 8-bit block, plus a total shift relative to the PTE.
171 static bool arm_v7s_pte_is_cont(arm_v7s_iopte pte, int lvl);
184 static arm_v7s_iopte to_mtk_iopte(phys_addr_t paddr, arm_v7s_iopte pte) in to_mtk_iopte() argument
187 pte |= ARM_V7S_ATTR_MTK_PA_BIT32; in to_mtk_iopte()
189 pte |= ARM_V7S_ATTR_MTK_PA_BIT33; in to_mtk_iopte()
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/linux/arch/powerpc/kvm/
H A Dtrace_pr.h64 TP_PROTO(struct hpte_cache *pte),
65 TP_ARGS(pte),
77 __entry->host_vpn = pte->host_vpn;
78 __entry->pfn = pte->pfn;
79 __entry->eaddr = pte->pte.eaddr;
80 __entry->vpage = pte->pte.vpage;
81 __entry->raddr = pte->pte.raddr;
82 __entry->flags = (pte->pte.may_read ? 0x4 : 0) |
83 (pte->pte.may_write ? 0x2 : 0) |
84 (pte->pte.may_execute ? 0x1 : 0);
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H A Dbook3s_32_mmu.c70 struct kvmppc_pte *pte, bool data,
84 struct kvmppc_pte pte; in kvmppc_mmu_book3s_32_ea_to_vp() local
86 if (!kvmppc_mmu_book3s_32_xlate_bat(vcpu, eaddr, &pte, data, false)) in kvmppc_mmu_book3s_32_ea_to_vp()
87 return pte.vpage; in kvmppc_mmu_book3s_32_ea_to_vp()
128 struct kvmppc_pte *pte, bool data, in kvmppc_mmu_book3s_32_xlate_bat() argument
160 pte->vpage = (((u64)eaddr >> 12) & 0xffff) | vsid; in kvmppc_mmu_book3s_32_xlate_bat()
162 pte->raddr = bat->brpn | (eaddr & ~bat->bepi_mask); in kvmppc_mmu_book3s_32_xlate_bat()
163 pte->may_read = bat->pp; in kvmppc_mmu_book3s_32_xlate_bat()
164 pte->may_write = bat->pp > 1; in kvmppc_mmu_book3s_32_xlate_bat()
165 pte->may_execute = true; in kvmppc_mmu_book3s_32_xlate_bat()
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H A Dbook3s_pr_papr.c92 unsigned long pte[2]; in kvmppc_h_pr_remove() local
98 if (copy_from_user(pte, (void __user *)pteg, sizeof(pte))) in kvmppc_h_pr_remove()
100 pte[0] = be64_to_cpu((__force __be64)pte[0]); in kvmppc_h_pr_remove()
101 pte[1] = be64_to_cpu((__force __be64)pte[1]); in kvmppc_h_pr_remove()
104 if ((pte[0] & HPTE_V_VALID) == 0 || in kvmppc_h_pr_remove()
105 ((flags & H_AVPN) && (pte[0] & ~0x7fUL) != avpn) || in kvmppc_h_pr_remove()
106 ((flags & H_ANDCOND) && (pte[0] & avpn) != 0)) in kvmppc_h_pr_remove()
113 rb = compute_tlbie_rb(pte[0], pte[1], pte_index); in kvmppc_h_pr_remove()
117 kvmppc_set_gpr(vcpu, 4, pte[0]); in kvmppc_h_pr_remove()
118 kvmppc_set_gpr(vcpu, 5, pte[1]); in kvmppc_h_pr_remove()
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/linux/mm/
H A Dpage_vma_mapped.c24 pvmw->pte = pte_offset_map_lock(pvmw->vma->vm_mm, pvmw->pmd, in map_pte()
27 return !!pvmw->pte; in map_pte()
33 * It is important to return the ptl corresponding to pte, in map_pte()
39 pvmw->pte = pte_offset_map_rw_nolock(pvmw->vma->vm_mm, pvmw->pmd, in map_pte()
41 if (!pvmw->pte) in map_pte()
44 ptent = ptep_get(pvmw->pte); in map_pte()
77 pte_unmap_unlock(pvmw->pte, *ptlp); in map_pte()
87 * mapped at the @pvmw->pte
88 * @pvmw: page_vma_mapped_walk struct, includes a pair pte and pfn range
90 * @pte_nr: the number of small pages described by @pvmw->pte.
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/linux/arch/parisc/kernel/
H A Dentry.S380 /* Look up a PTE in a 2-Level scheme (faulting at each
386 .macro L2_ptep pmd,pte,index,va,fault
394 copy %r0,\pte
402 shladd \index,BITS_PER_PTE_ENTRY,\pmd,\pmd /* pmd is now pte */
405 /* Look up PTE in a 3-Level scheme. */
406 .macro L3_ptep pgd,pte,index,va,fault
408 copy %r0,\pte
414 L2_ptep \pgd,\pte,\index,\va,\fault
418 .macro ptl_lock spc,ptp,pte,tmp,tmp1,fault
425 LDREG 0(\ptp),\pte
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/linux/arch/arm/include/asm/
H A Dpgalloc.h41 #define pud_populate(mm,pmd,pte) do { } while (0) argument
43 #define pud_populate(mm,pmd,pte) BUG() argument
50 static inline void clean_pte_table(pte_t *pte) in clean_pte_table() argument
52 clean_dcache_area(pte + PTE_HWTABLE_PTRS, PTE_HWTABLE_SIZE); in clean_pte_table()
56 * Allocate one PTE table.
58 * This actually allocates two hardware PTE tables, but we wrap this up
80 pte_t *pte = __pte_alloc_one_kernel(mm); in pte_alloc_one_kernel() local
82 if (pte) in pte_alloc_one_kernel()
83 clean_pte_table(pte); in pte_alloc_one_kernel()
85 return pte; in pte_alloc_one_kernel()
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