| /linux/arch/powerpc/include/asm/ |
| H A D | mpc52xx_psc.h | 5 * PSCs. Theses are shared between multiple drivers since a PSC can be
34 /* Programmable Serial Controller (PSC) status register bits */
49 /* PSC Command values */
62 /* PSC TxRx FIFO status bits */
71 /* PSC interrupt status/mask bits */
85 /* PSC input port change bits */
91 /* PSC acr bits */
95 /* PSC output port bits */
99 /* PSC mode fields */
154 u8 mode; /* PSC + 0x00 */
[all …]
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| /linux/drivers/spi/ |
| H A D | spi-mpc52xx-psc.c | 3 * MPC52xx PSC in SPI mode driver.
26 #define MCLK 20000000 /* PSC port MClk in hz */
30 struct mpc52xx_psc __iomem *psc; member
64 struct mpc52xx_psc __iomem *psc = mps->psc; in mpc52xx_psc_spi_activate_cs() local
68 sicr = in_be32(&psc->sicr); in mpc52xx_psc_spi_activate_cs()
84 out_be32(&psc->sicr, sicr); in mpc52xx_psc_spi_activate_cs()
87 * Because psc->ccr is defined as 16bit register instead of 32bit in mpc52xx_psc_spi_activate_cs()
90 ccr = in_be16((u16 __iomem *)&psc->ccr); in mpc52xx_psc_spi_activate_cs()
96 out_be16((u16 __iomem *)&psc->ccr, ccr); in mpc52xx_psc_spi_activate_cs()
108 struct mpc52xx_psc __iomem *psc = mps->psc; in mpc52xx_psc_spi_transfer_rxtx() local
[all …]
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| /linux/arch/powerpc/boot/dts/ |
| H A D | pdm360ng.dts | 136 psc@11000 {
137 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
140 psc@11100 {
141 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
144 psc@11200 {
145 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
148 psc@11300 {
149 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
152 psc@11400 {
153 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
[all …]
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| H A D | cm5200.dts | 26 psc@2000 { // PSC1
27 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
30 psc@2200 { // PSC2
31 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
34 psc@2400 { // PSC3
35 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
38 psc@2600 { // PSC4
42 psc@2800 { // PSC5
46 psc@2c00 { // PSC6
47 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
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| H A D | o2d.dtsi | 32 psc@2000 { // PSC1
33 compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi";
39 psc@2200 { // PSC2
43 psc@2400 { // PSC3
47 psc@2600 { // PSC4
48 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
51 psc@2800 { // PSC5
52 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
55 psc@2c00 { // PSC6
|
| H A D | a4m072.dts | 42 psc@2000 {
43 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
48 psc@2200 {
49 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
54 psc@2400 {
55 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
60 psc@2600 {
64 psc@2800 {
68 psc@2c00 {
69 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
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| H A D | pcm030.dts | 26 audioplatform: psc@2000 { /* PSC1 in ac97 mode */
27 compatible = "mpc5200b-psc-ac97","fsl,mpc5200b-psc-ac97";
32 psc@2200 {
36 psc@2400 { /* PSC3 in UART mode */
37 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
41 psc@2600 {
46 psc@2800 {
50 psc@2c00 { /* PSC6 in UART mode */
51 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
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| H A D | uc101.dts | 46 psc@2000 { // PSC1
47 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
50 psc@2200 { // PSC2
51 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
54 psc@2400 { // PSC3
58 psc@2600 { // PSC4
62 psc@2800 { // PSC5
66 psc@2c00 { // PSC6
67 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
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| H A D | motionpro.dts | 31 psc@2000 { // PSC1
32 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
36 psc@2200 { // PSC2
37 compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi";
41 psc@2400 { // PSC3
45 psc@2600 { // PSC4
49 psc@2800 { // PSC5
50 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
53 psc@2c00 { // PSC6
|
| H A D | lite5200b.dts | 39 psc@2000 { // PSC1
40 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
44 psc@2200 { // PSC2
48 psc@2400 { // PSC3
52 psc@2600 { // PSC4
56 psc@2800 { // PSC5
60 psc@2c00 { // PSC6
66 // compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97";
72 // compatible = "fsl,mpc5200b-psc-i2s"; //not 5200 compatible
78 // compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi";
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| H A D | mpc5121.dtsi | 346 /* 512x PSCs are not 52xx PSC compatible */
349 psc@11000 {
350 compatible = "fsl,mpc5121-psc";
361 psc@11100 {
362 compatible = "fsl,mpc5121-psc";
373 psc@11200 {
374 compatible = "fsl,mpc5121-psc";
385 psc@11300 {
386 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
397 psc@11400 {
[all …]
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| H A D | pcm032.dts | 28 psc@2000 { /* PSC1 is ac97 */
29 compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97";
34 psc@2200 {
38 psc@2400 { /* PSC3 in UART mode */
39 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
43 psc@2600 {
48 psc@2800 {
52 psc@2c00 { /* PSC6 in UART mode */
53 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
| H A D | mpc5200b.dtsi | 182 psc1: psc@2000 { // PSC1
183 compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
188 psc2: psc@2200 { // PSC2
189 compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
194 psc3: psc@2400 { // PSC3
195 compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
200 psc4: psc@2600 { // PSC4
201 compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
206 psc5: psc@2800 { // PSC5
207 compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
[all …]
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| H A D | a3m071.dts | 39 psc@2000 {
40 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
45 psc@2200 {
49 psc@2400 {
53 psc@2600 {
57 psc@2800 {
61 psc@2c00 { // PSC6
62 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
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| /linux/Documentation/devicetree/bindings/powerpc/fsl/ |
| H A D | mpc5121-psc.txt | 1 MPC5121 PSC Device Tree Bindings
3 PSC in UART mode
6 For PSC in UART mode the needed PSC serial devices
7 are specified by fsl,mpc5121-psc-uart nodes in the
8 fsl,mpc5121-immr SoC node. Additionally the PSC FIFO
9 Controller node fsl,mpc5121-psc-fifo is required there:
11 fsl,mpc512x-psc-uart nodes
15 - compatible : Should contain "fsl,<soc>-psc-uart" and "fsl,<soc>-psc"
17 - reg : Offset and length of the register set for the PSC device
19 PSC FIFO Controller and b is a field that represents an
[all …]
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| H A D | mpc5200.txt | 38 end of the compatible field. ie. A PSC in i2s mode would specify
39 "fsl,mpc5200-psc-i2s", not "fsl,mpc5200-i2s". This convention is chosen to
40 avoid naming conflicts with non-psc devices providing the same
41 function. For example, "fsl,mpc5200-spi" and "fsl,mpc5200-psc-spi" describe
42 the mpc5200 simple spi device and a PSC spi mode respectively.
90 serial@<addr> fsl,mpc5200-psc-uart PSC in serial mode
91 i2s@<addr> fsl,mpc5200-psc-i2s PSC in i2s mode
92 ac97@<addr> fsl,mpc5200-psc-ac97 PSC in ac97 mode
93 spi@<addr> fsl,mpc5200-psc-spi PSC in spi mode
94 irda@<addr> fsl,mpc5200-psc-irda PSC in IrDA mode
[all …]
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| /linux/drivers/clk/keystone/ |
| H A D | gate.c | 17 /* PSC register offsets */
25 /* PSC module states */
44 * struct clk_psc_data - PSC data
45 * @control_base: Base address for a PSC control
46 * @domain_base: Base address for a PSC domain
47 * @domain_id: PSC domain id number
56 * struct clk_psc - PSC clock structure
57 * @hw: clk_hw for the psc
58 * @psc_data: PSC driver specific data
106 struct clk_psc *psc = to_clk_psc(hw); in keystone_clk_is_enabled() local
[all …]
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| /linux/drivers/clk/davinci/ |
| H A D | psc.c | 3 * Clock driver for TI Davinci PSC controllers
12 * And: arch/arm/mach-davinci/psc.c
31 #include "psc.h"
33 /* PSC register offsets */
42 /* PSC module states */
70 * @regmap: PSC MMIO region
227 * @regmap: PSC MMIO region
228 * @md: local PSC number
308 struct davinci_psc_data *psc = to_davinci_psc_data(rcdev); in davinci_psc_reset_assert() local
309 struct clk *clk = psc->clk_data.clks[id]; in davinci_psc_reset_assert()
[all …]
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| /linux/arch/arm/boot/dts/ti/keystone/ |
| H A D | keystone-k2hk-clocks.dtsi | 55 compatible = "ti,keystone,psc-clock";
65 compatible = "ti,keystone,psc-clock";
75 compatible = "ti,keystone,psc-clock";
85 compatible = "ti,keystone,psc-clock";
95 compatible = "ti,keystone,psc-clock";
105 compatible = "ti,keystone,psc-clock";
115 compatible = "ti,keystone,psc-clock";
125 compatible = "ti,keystone,psc-clock";
135 compatible = "ti,keystone,psc-clock";
145 compatible = "ti,keystone,psc-clock";
[all …]
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| H A D | keystone-k2l-clocks.dtsi | 46 compatible = "ti,keystone,psc-clock";
56 compatible = "ti,keystone,psc-clock";
66 compatible = "ti,keystone,psc-clock";
76 compatible = "ti,keystone,psc-clock";
86 compatible = "ti,keystone,psc-clock";
96 compatible = "ti,keystone,psc-clock";
106 compatible = "ti,keystone,psc-clock";
116 compatible = "ti,keystone,psc-clock";
126 compatible = "ti,keystone,psc-clock";
136 compatible = "ti,keystone,psc-clock";
[all …]
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| H A D | keystone-clocks.dtsi | 162 compatible = "ti,keystone,psc-clock";
173 compatible = "ti,keystone,psc-clock";
183 compatible = "ti,keystone,psc-clock";
194 compatible = "ti,keystone,psc-clock";
204 compatible = "ti,keystone,psc-clock";
214 compatible = "ti,keystone,psc-clock";
224 compatible = "ti,keystone,psc-clock";
234 compatible = "ti,keystone,psc-clock";
244 compatible = "ti,keystone,psc-clock";
254 compatible = "ti,keystone,psc-clock";
[all …]
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| /linux/arch/powerpc/boot/ |
| H A D | mpc52xx-psc.c | 3 * MPC5200 PSC serial console support.
18 /* Programmable Serial Controller (PSC) status register bits */
27 static void *psc; variable
31 /* Assume the firmware has already configured the PSC into in psc_open()
38 while (!(in_be16(psc + MPC52xx_PSC_SR) & MPC52xx_PSC_SR_TXRDY)) ; in psc_putc()
39 out_8(psc + MPC52xx_PSC_BUFFER, c); in psc_putc()
44 return (in_be16(psc + MPC52xx_PSC_SR) & MPC52xx_PSC_SR_RXRDY) != 0; in psc_tstc()
49 while (!(in_be16(psc + MPC52xx_PSC_SR) & MPC52xx_PSC_SR_RXRDY)) ; in psc_getc()
50 return in_8(psc + MPC52xx_PSC_BUFFER); in psc_getc()
55 /* Get the base address of the psc registers */ in mpc5200_psc_console_init()
[all …]
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| /linux/arch/m68k/mac/ |
| H A D | psc.c | 3 * Apple Peripheral System Controller (PSC)
5 * The PSC is used on the AV Macs to control IO functions not handled
33 volatile __u8 *psc; variable
34 EXPORT_SYMBOL_GPL(psc);
44 if (!psc) in psc_debug_dump()
48 printk(KERN_DEBUG "PSC #%d: IFR = 0x%02X IER = 0x%02X\n", in psc_debug_dump()
56 * Try to kill all DMA channels on the PSC. Not sure how this his
74 * Initialize the PSC. For now this just involves shutting down all
85 psc = NULL; in psc_init()
90 * The PSC is always at the same spot, but using psc in psc_init()
[all …]
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| /linux/drivers/tty/serial/ |
| H A D | mpc52xx_uart.c | 3 * Driver for the PSC of the Freescale MPC52xx PSCs configured as UARTs.
62 * psc->mpc52xx_psc_imr
75 #define PSC(port) ((struct mpc52xx_psc __iomem *)((port)->membase)) macro
83 /* PSC fifo operations for isolating differences between 52xx and 512x */
124 static inline void mpc52xx_set_divisor(struct mpc52xx_psc __iomem *psc, in mpc52xx_set_divisor() argument
128 out_be16(&psc->mpc52xx_psc_clock_select, prescaler); in mpc52xx_set_divisor()
129 out_8(&psc->ctur, divisor >> 8); in mpc52xx_set_divisor()
130 out_8(&psc->ctlr, divisor & 0xff); in mpc52xx_set_divisor()
135 return in_be16(&PSC(port)->mpc52xx_psc_status); in mpc52xx_psc_get_status()
140 return in_8(&PSC(port)->mpc52xx_psc_ipcr); in mpc52xx_psc_get_ipcr()
[all …]
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| /linux/drivers/staging/rtl8192e/rtl8192e/ |
| H A D | rtl_ps.c | 103 struct rt_pwr_save_ctrl *psc = (struct rt_pwr_save_ctrl *) in _rtl92e_ps_update_rf_state() local
106 psc->bSwRfProcessing = true; in _rtl92e_ps_update_rf_state()
107 rtl92e_set_rf_state(dev, psc->eInactivePowerState, RF_CHANGE_BY_IPS); in _rtl92e_ps_update_rf_state()
109 psc->bSwRfProcessing = false; in _rtl92e_ps_update_rf_state()
115 struct rt_pwr_save_ctrl *psc = (struct rt_pwr_save_ctrl *) in rtl92e_ips_enter() local
120 if (rt_state == rf_on && !psc->bSwRfProcessing && in rtl92e_ips_enter()
122 psc->eInactivePowerState = rf_off; in rtl92e_ips_enter()
130 struct rt_pwr_save_ctrl *psc = (struct rt_pwr_save_ctrl *) in rtl92e_ips_leave() local
135 if (rt_state != rf_on && !psc->bSwRfProcessing && in rtl92e_ips_leave()
137 psc->eInactivePowerState = rf_on; in rtl92e_ips_leave()
[all …]
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