Home
last modified time | relevance | path

Searched full:pl310 (Results 1 – 25 of 68) sorted by relevance

123

/linux/Documentation/devicetree/bindings/cache/
H A Dl2c2x0.yaml14 PL220/PL310 and variants) based level 2 cache controller. All these various
34 - arm,pl310-cache
37 # DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
38 - bcm,bcm11351-a2-pl310-cache
42 - brcm,bcm11351-a2-pl310-cache
53 # with arm,pl310-cache controller.
55 - const: arm,pl310-cache
109 I/O coherent mode. Valid only when the arm,pl310-cache compatible
157 description: The default behavior of the L220 or PL310 cache
166 description: enable parity checking on the L2 cache (L220 or PL310).
[all …]
/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2p-ca9.dts167 compatible = "arm,pl310-cache";
227 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
236 /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
272 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
279 /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
286 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
293 /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
H A Darm-realview-pbx-a9.dts64 compatible = "arm,pl310-cache";
H A Dvexpress-v2p-ca5s.dts131 compatible = "arm,pl310-cache";
/linux/arch/arm/mm/
H A DKconfig978 or PL310 cache controller, but where its use is optional.
1001 of the L220 and PL310 outer cache controllers.
1006 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1008 The PL310 L2 cache controller implements three types of Clean &
1014 is not correctly implemented in PL310 prior to r2p0 (fixed in r2p0)
1018 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1020 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1022 PL310 can handle normal accesses while it is in progress. Under very
1024 PL310 treats a cacheable write transaction during a Clean &
1029 bool "PL310 errata: cache sync operation may be faulty"
[all …]
H A Dcache-l2x0.c439 * 588369: PL310 R0P0->R1P0, fixed R2P0.
447 * 727915: PL310 R2P0->R3P0, fixed R3P1.
453 * 752271: PL310 R3P0->R3P1-50REL0, fixed R3P2.
458 * 753970: PL310 R3P0, fixed R3P1.
463 * 769419: PL310 R0P0->R3P1, fixed R3P2.
574 /* restore pl310 setup */ in l2c310_configure()
1325 * coherent, and potentially harmful in certain situations (PCIe/PL310
1751 L2C_ID("arm,pl310-cache", of_l2c310_data),
1752 L2C_ID("brcm,bcm11351-a2-pl310-cache", of_bcm_l2x0_data),
1757 L2C_ID("bcm,bcm11351-a2-pl310-cache", of_bcm_l2x0_data),
[all …]
H A Dcache-tauros3.h15 * Marvell Tauros3 L2CC is compatible with PL310 r0p0
H A Dcache-l2x0-pmu.c30 * The L220/PL310 PMU has two equivalent counters, Counter1 and Counter0.
479 * which events to display, as the PL310 PMU supports a superset of in l2x0_pmu_register()
/linux/arch/arm/mach-imx/
H A Dpm-imx6.c157 .pl310_compat = "arm,pl310-cache",
167 .pl310_compat = "arm,pl310-cache",
177 .pl310_compat = "arm,pl310-cache",
187 .pl310_compat = "arm,pl310-cache",
197 .pl310_compat = "arm,pl310-cache",
553 pr_warn("%s: failed to get pl310-cache base %d!\n", in imx6q_suspend_init()
H A Dsystem.c92 np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache"); in imx_init_l2cache()
/linux/arch/arm/mach-mvebu/
H A Dcoherency.c177 * We should switch the PL310 to I/O coherency mode only if in armada_375_380_coherency_init()
184 * Add the PL310 property "arm,io-coherent". This makes sure the in armada_375_380_coherency_init()
190 for_each_compatible_node(cache_dn, NULL, "arm,pl310-cache") { in armada_375_380_coherency_init()
/linux/drivers/soc/tegra/
H A DKconfig22 ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
36 ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
/linux/arch/arm/boot/dts/axis/
H A Dartpec6.dtsi61 next-level-cache = <&pl310>;
68 next-level-cache = <&pl310>;
133 pl310: cache-controller@faf10000 { label
134 compatible = "arm,pl310-cache";
/linux/arch/arm/mach-ux500/
H A Dcpu-db8500.c35 np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache"); in ux500_l2x0_unlock()
45 * already enabled, so we do it right here instead. The PL310 has in ux500_l2x0_unlock()
/linux/arch/arm/mach-socfpga/
H A DKconfig19 select PL310_ERRATA_753970 if PL310
/linux/arch/arm/boot/dts/nxp/vf/
H A Dvf610.dtsi13 compatible = "arm,pl310-cache";
/linux/arch/arm/mach-berlin/
H A Dberlin.c22 * Note: 88DE3005 (Armada 1500-mini) uses pl310 l2cc
/linux/arch/arm/mach-highbank/
H A Dsmc.S11 * used to modify the PL310 secure registers.
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm21664.dtsi40 compatible = "arm,pl310-cache";
H A Dbcm63138.dtsi85 compatible = "arm,pl310-cache";
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dst,stih407-irq-syscfg.yaml14 Management), and PL310 L2 Cache IRQs are controlled using System
/linux/arch/arm/mach-omap2/
H A Domap-smc.S16 * used to modify the PL310 secure registers.
/linux/arch/arm/boot/dts/hpe/
H A Dhpe-gxp.dtsi49 compatible = "arm,pl310-cache";
/linux/arch/arm/boot/dts/calxeda/
H A Dhighbank.dts136 compatible = "arm,pl310-cache";
/linux/arch/arm/boot/dts/unisoc/
H A Drda8810pl.dtsi142 compatible = "arm,pl310-cache";

123