| /freebsd/sys/contrib/dev/mediatek/mt76/mt7915/ |
| H A D | debugfs.c | 1 // SPDX-License-Identifier: ISC
29 dev->ibf = !!val; in mt7915_implicit_txbf_set()
39 *val = dev->ibf; in mt7915_implicit_txbf_get()
52 struct mt7915_phy *phy = file->private_data; in mt7915_sys_recovery_set() local
53 struct mt7915_dev *dev = phy->dev; in mt7915_sys_recovery_set()
54 bool band = phy->mt76->band_idx; in mt7915_sys_recovery_set()
60 return -EINVAL; in mt7915_sys_recovery_set()
63 return -EFAULT; in mt7915_sys_recovery_set()
65 if (count && buf[count - 1] == '\n') in mt7915_sys_recovery_set()
66 buf[count - 1] = '\0'; in mt7915_sys_recovery_set()
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| /freebsd/tools/tools/net80211/wlantxtime/ |
| H A D | wlantxtime.c | 1 /*-
2 * Copyright (c) 2007-2009 Sam Leffler, Errno Consulting
28 * IEEE 802.11 PHY-related support.
51 uint8_t phy; /* CCK/OFDM/TURBO */ member
72 exit(-1); \
84 exit(-1); in panic()
102 [0] = { .phy = CCK, 1000, 0x00, B(2), 0 },/* 1 Mb */
103 [1] = { .phy = CCK, 2000, 0x04, B(4), 1 },/* 2 Mb */
104 [2] = { .phy = CCK, 5500, 0x04, B(11), 1 },/* 5.5 Mb */
105 [3] = { .phy = CCK, 11000, 0x04, B(22), 1 },/* 11 Mb */
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| /freebsd/sys/dev/etherswitch/ar40xx/ |
| H A D | ar40xx_phy.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
82 int phy; in ar40xx_phy_tick() local
89 * Loop over; update phy port status here in ar40xx_phy_tick()
91 for (phy = 0; phy < AR40XX_NUM_PHYS; phy++) { in ar40xx_phy_tick()
93 * Port here is PHY, not port! in ar40xx_phy_tick()
95 reg = AR40XX_REG_READ(sc, AR40XX_REG_PORT_STATUS(phy + 1)); in ar40xx_phy_tick()
97 mii = device_get_softc(sc->sc_phys.miibus[phy]); in ar40xx_phy_tick()
101 * status. We may need to clear ATU / change phy config. in ar40xx_phy_tick()
104 (mii->mii_media_status & IFM_ACTIVE) == 0) { in ar40xx_phy_tick()
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| H A D | ar40xx_hw_psgmii.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
76 * Routines that control the ess-psgmii block - the interconnect
77 * between the ess-switch and the external multi-port PHY
85 bus_space_write_4(sc->sc_psgmii_mem_tag, sc->sc_psgmii_mem_handle, in ar40xx_hw_psgmii_reg_write()
87 bus_space_barrier(sc->sc_psgmii_mem_tag, sc->sc_psgmii_mem_handle, in ar40xx_hw_psgmii_reg_write()
88 0, sc->sc_psgmii_mem_size, BUS_SPACE_BARRIER_WRITE); in ar40xx_hw_psgmii_reg_write()
96 bus_space_barrier(sc->sc_psgmii_mem_tag, sc->sc_psgmii_mem_handle, in ar40xx_hw_psgmii_reg_read()
97 0, sc->sc_psgmii_mem_size, BUS_SPACE_BARRIER_READ); in ar40xx_hw_psgmii_reg_read()
98 ret = bus_space_read_4(sc->sc_psgmii_mem_tag, sc->sc_psgmii_mem_handle, in ar40xx_hw_psgmii_reg_read()
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| /freebsd/sys/contrib/device-tree/Bindings/phy/ |
| H A D | ti,phy-gmii-sel.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/phy/ti,phy-gmii-sel.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: CPSW Port's Interface Mode Selection PHY
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 The interface mode is selected by configuring the MII mode selection register(s)
17 (GMII_SEL) in the System Control Module chapter (SCM). GMII_SEL register(s) and
20 +--------------+
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| H A D | ti-phy-gmii-sel.txt | 1 CPSW Port's Interface Mode Selection PHY Tree Bindings
2 -----------------------------------------------
6 The interface mode is selected by configuring the MII mode selection register(s)
7 (GMII_SEL) in the System Control Module chapter (SCM). GMII_SEL register(s) and
10 +--------------+
11 +-------------------------------+ |SCM |
12 | CPSW | | +---------+ |
13 | +--------------------------------+gmii_sel | |
14 | | | | +---------+ |
15 | +----v---+ +--------+ | +--------------+
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| H A D | nvidia,tegra20-usb-phy.txt | 1 Tegra SOC USB PHY
3 The device node for Tegra SOC USB PHY:
6 - compatible : For Tegra20, must contain "nvidia,tegra20-usb-phy".
7 For Tegra30, must contain "nvidia,tegra30-usb-phy". Otherwise, must contain
8 "nvidia,<chip>-usb-phy" plus at least one of the above, where <chip> is
10 - reg : Defines the following set of registers, in the order listed:
11 - The PHY's own register set.
13 - The register set of the PHY containing the UTMI pad control registers.
14 Present if-and-only-if phy_type == utmi.
15 - phy_type : Should be one of "utmi", "ulpi" or "hsic".
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| H A D | phy-mtk-tphy.txt | 1 MediaTek T-PHY binding
2 --------------------------
4 T-phy controller supports physical layer functionality for a number of
8 - compatible : should be one of
9 "mediatek,generic-tphy-v1"
10 "mediatek,generic-tphy-v2"
11 "mediatek,mt2701-u3phy" (deprecated)
12 "mediatek,mt2712-u3phy" (deprecated)
13 "mediatek,mt8173-u3phy";
14 make use of "mediatek,generic-tphy-v1" on mt2701 instead and
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| H A D | phy-mvebu-comphy.txt | 2 --------------------
12 - compatible: should be one of:
13 * "marvell,comphy-cp110" for Armada 7k/8k
14 * "marvell,comphy-a3700" for Armada 3700
15 - reg: should contain the COMPHY register(s) location(s) and length(s).
17 * 4 entries for Armada 3700 along with the corresponding reg-names
23 - marvell,system-controller: should contain a phandle to the system
25 - #address-cells: should be 1.
26 - #size-cells: should be 0.
30 - clocks: pointers to the reference clocks for this device (CP110 only),
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| /freebsd/sys/dev/axgbe/ |
| H A D | xgbe-mdio.c | 4 * Copyright (c) 2014-2016,2020 Advanced Micro Devices, Inc.
116 #include "xgbe-common.h"
179 switch (pdata->an_mode) { in xgbe_an_enable_interrupts()
204 pdata->hw_if.set_speed(pdata, SPEED_10000); in xgbe_kr_mode()
206 /* Call PHY implementation support to complete rate change */ in xgbe_kr_mode()
207 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KR); in xgbe_kr_mode()
214 pdata->hw_if.set_speed(pdata, SPEED_2500); in xgbe_kx_2500_mode()
216 /* Call PHY implementation support to complete rate change */ in xgbe_kx_2500_mode()
217 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KX_2500); in xgbe_kx_2500_mode()
224 pdata->hw_if.set_speed(pdata, SPEED_1000); in xgbe_kx_1000_mode()
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| H A D | xgbe-phy-v2.c | 116 #include "xgbe-common.h"
142 /* Rate-change complete wait/retry count */
153 /* SFP port max PHY probe retries */
275 * Optical specification compliance - denotes wavelength
306 ((_x)->extd[XGBE_SFP_EXTD_SFF_8472] && \
307 !((_x)->extd[XGBE_SFP_EXTD_DIAG] & XGBE_SFP_EXTD_DIAG_ADDR_CHANGE))
314 #define XGBE_BEL_FUSE_VENDOR "BEL-FUSE "
315 #define XGBE_BEL_FUSE_PARTNO "1GBT-SFP06 "
326 /* MDIO PHY reset types */
334 /* Re-driver related definitions */
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| /freebsd/sys/contrib/dev/mediatek/mt76/mt7996/ |
| H A D | debugfs.c | 1 // SPDX-License-Identifier: ISC
31 dev->ibf = !!val; in mt7996_implicit_txbf_set()
41 *val = dev->ibf; in mt7996_implicit_txbf_get()
54 struct mt7996_dev *dev = file->private_data; in mt7996_sys_recovery_set()
60 return -EINVAL; in mt7996_sys_recovery_set()
63 return -EFAULT; in mt7996_sys_recovery_set()
65 if (count && buf[count - 1] == '\n') in mt7996_sys_recovery_set()
66 buf[count - 1] = '\0'; in mt7996_sys_recovery_set()
72 return -EINVAL; in mt7996_sys_recovery_set()
76 return -EINVAL; in mt7996_sys_recovery_set()
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| /freebsd/sys/dev/mii/ |
| H A D | miivar.h | 3 /*-
4 * SPDX-License-Identifier: BSD-2-Clause
73 * PHY driver fills this in with active media status.
81 * Functions provided by the PHY to perform various functions.
92 #define MII_TICK 1 /* once-per-second tick */
97 * Each PHY driver's softc has one of these as the first member.
104 LIST_ENTRY(mii_softc) mii_list; /* entry on parent's PHY list */
106 uint32_t mii_mpd_oui; /* the PHY's OUI (MII_OUI())*/
107 uint32_t mii_mpd_model; /* the PHY's model (MII_MODEL())*/
108 uint32_t mii_mpd_rev; /* the PHY's revision (MII_REV())*/
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| H A D | miidevs | 3 /*-
35 * For a complete list see http://standards-oui.ieee.org/
39 * IEEE 802.3u-1995, subclause 22.2.4.3.1, figure 22-12, depicts the right
40 * mapping; the bit positions are defined in IEEE 802-1990, figure 5.2.
41 * (There is a formal 802.3 interpretation, number 1-07/98 of July 09 1998,
69 oui PMCSIERRA 0x00e004 PMC-Sierra
81 /* Some Intel 82553's use an alternative OUI. */
84 /* Some VIA 6122's use an alternative OUI. */
106 /* Don't know what's going on here. */
110 oui xxPMCSIERRA 0x0009c0 PMC-Sierra
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| /freebsd/sys/dev/etherswitch/arswitch/ |
| H A D | arswitch_phy.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2011-2012 Stefan Bethke.
67 * to the PHY space itself, rather than through the switch
71 arswitch_readphy_external(device_t dev, int phy, int reg) in arswitch_readphy_external() argument
79 ret = (MDIO_READREG(device_get_parent(dev), phy, reg)); in arswitch_readphy_external()
81 "%s: phy=0x%08x, reg=0x%08x, ret=0x%08x\n", in arswitch_readphy_external()
82 __func__, phy, reg, ret); in arswitch_readphy_external()
89 arswitch_writephy_external(device_t dev, int phy, int reg, int data) in arswitch_writephy_external() argument
96 (void) MDIO_WRITEREG(device_get_parent(dev), phy, in arswitch_writephy_external()
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| H A D | arswitch.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2011-2012 Stefan Bethke.
82 static inline int arswitch_portforphy(int phy);
90 static int arswitch_setled(struct arswitch_softc *sc, int phy, int led,
102 sc->page = -1; in arswitch_probe()
106 sc->chip_rev = (id & AR8X16_MASK_CTRL_REV_MASK); in arswitch_probe()
107 sc->chip_ver = (id & AR8X16_MASK_CTRL_VER_MASK) >> AR8X16_MASK_CTRL_VER_SHIFT; in arswitch_probe()
111 sc->sc_switchtype = AR8X16_SWITCH_AR8216; in arswitch_probe()
115 sc->sc_switchtype = AR8X16_SWITCH_AR8226; in arswitch_probe()
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| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | ethernet-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <davem@davemloft.net>
19 local-mac-address:
22 $ref: /schemas/types.yaml#/definitions/uint8-array
26 mac-address:
31 local-mac-address property.
32 $ref: /schemas/types.yaml#/definitions/uint8-array
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| /freebsd/sys/contrib/dev/mediatek/mt76/mt7615/ |
| H A D | debugfs.c | 1 // SPDX-License-Identifier: ISC
11 mt76_wr(dev, dev->mt76.debugfs_reg, val); in mt7615_reg_set()
23 *val = mt76_rr(dev, dev->mt76.debugfs_reg); in mt7615_reg_get()
57 ret = mt76_connac_mcu_chip_config(&dev->mt76); in mt7615_config()
74 mt7615_mac_set_scs(&dev->phy, val); in mt7615_scs_set()
87 *val = dev->phy.scs_en; in mt7615_scs_get()
99 struct mt76_connac_pm *pm = &dev->pm; in mt7615_pm_set()
105 if (!mt7615_firmware_offload(dev) || mt76_is_usb(&dev->mt76)) in mt7615_pm_set()
106 return -EOPNOTSUPP; in mt7615_pm_set()
108 mutex_lock(&dev->mt76.mutex); in mt7615_pm_set()
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| /freebsd/sys/cam/scsi/ |
| H A D | smp_all.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
32 * $Id: //depot/users/kenm/FreeBSD-test/sys/cam/scsi/smp_all.c#4 $
92 {SMP_FR_PHY_DOES_NOT_EXIST, "Phy Does Not Exist"},
94 {SMP_FR_PHY_DOES_NOT_SUP_SATA, "Phy Does Not Support SATA"},
95 {SMP_FR_UNKNOWN_PHY_OP, "Unknown Phy Operation"},
96 {SMP_FR_UNKNOWN_PHY_TEST_FUNC, "Unknown Phy Test Function"},
97 {SMP_FR_PHY_TEST_FUNC_INPROG, "Phy Test Function In Progress"},
98 {SMP_FR_PHY_VACANT, "Phy Vacant"},
99 {SMP_FR_UNKNOWN_PHY_EVENT_SRC, "Unknown Phy Event Source"},
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| /freebsd/sys/dev/etherswitch/mtkswitch/ |
| H A D | mtkswitch.c | 1 /*-
3 * Copyright (c) 2011-2012 Stefan Bethke.
69 static inline int mtkswitch_portforphy(int phy);
75 { "ralink,rt3050-esw", MTK_SWITCH_RT3050 },
76 { "ralink,rt3352-esw", MTK_SWITCH_RT3352 },
77 { "ralink,rt5350-esw", MTK_SWITCH_RT5350 },
78 { "mediatek,mt7620-gsw", MTK_SWITCH_MT7620 },
79 { "mediatek,mt7621-gsw", MTK_SWITCH_MT7621 },
80 { "mediatek,mt7628-esw", MTK_SWITCH_MT7628 },
95 switch_type = ofw_bus_search_compatible(dev, compat_data)->ocd_data; in mtkswitch_probe()
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| /freebsd/sys/dev/isci/scil/ |
| H A D | scif_sas_smp_phy.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0
9 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
22 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
28 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
69 //* P U B L I C M E T H O D S
74 * @brief This routine constructs a smp phy object for an expander phy and insert
75 * to owning expander device's smp_phy_list.
76 * @param[in] this_smp_phy The memory space to store a phy
77 * @param[in] owning_device The smp remote device that owns this smp phy.
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| H A D | scu_bios_definitions.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0
9 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
22 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
28 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
64 * stand-alone where the library is excluded. By excluding
169 * This field contains the size in bytes of the descriptor element(s)
208 * in APC mode, if ANY of the phy mask is non-zero,
212 * in MPC mode, if ALL of the phy masks are zero,
229 * This field indicates OEM's desired default
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| /freebsd/sys/dev/bwn/ |
| H A D | if_bwn_phy_g.c | 1 /*-
2 * Copyright (c) 2009-2010 Weongyo Jeong <weongyo@freebsd.org>
143 if (mac->mac_phy.hwpctl == 0 || mac->mac_phy.use_hwpctl == NULL) in bwn_has_hwpctl()
145 return (mac->mac_phy.use_hwpctl(mac)); in bwn_has_hwpctl()
151 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_g_attach()
152 struct bwn_phy *phy = &mac->mac_phy; in bwn_phy_g_attach() local
153 struct bwn_phy_g *pg = &phy->phy_g; in bwn_phy_g_attach()
165 device_printf((_dev), "NVRAM variable %s unreadable: " \ in bwn_phy_g_attach()
171 BWN_PHY_G_READVAR(sc->sc_dev, int8, BHND_NVAR_PA0ITSSIT, &bg); in bwn_phy_g_attach()
172 BWN_PHY_G_READVAR(sc->sc_dev, int16, BHND_NVAR_PA0B0, &pab0); in bwn_phy_g_attach()
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| /freebsd/sys/contrib/device-tree/Bindings/usb/ |
| H A D | exynos-usb.txt | 8 - compatible: should be "samsung,exynos4210-ehci" for USB 2.0
10 - reg: physical base address of the controller and length of memory mapped
12 - interrupts: interrupt number to the cpu.
13 - clocks: from common clock binding: handle to usb clock.
14 - clock-names: from common clock binding: Shall be "usbhost".
15 - phys: from the *Generic PHY* bindings; array specifying phy(s) used
17 - phy-names: from the *Generic PHY* bindings; array of the names for
18 each phy for the root ports, must be a subset of the following:
22 - samsung,vbus-gpio: if present, specifies the GPIO that
28 compatible = "samsung,exynos4210-ehci";
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| /freebsd/sys/contrib/device-tree/Bindings/net/dsa/ |
| H A D | sja1105.txt | 6 - compatible:
8 - "nxp,sja1105e"
9 - "nxp,sja1105t"
10 - "nxp,sja1105p"
11 - "nxp,sja1105q"
12 - "nxp,sja1105r"
13 - "nxp,sja1105s"
17 For example, SGMII can only be specified on port 4 of R and S devices,
18 and the non-SGMII devices, while pin-compatible, are not equal in terms
19 of support for RGMII internal delays (supported on P/Q/R/S, but not on
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