xref: /linux/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml (revision ec7336475d52575381149aa67f9526c2f6d45e0d) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/renesas,r9a09g077-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas RZ/T2H and RZ/N2H Pin and GPIO controller
8
9maintainers:
10  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
11
12description:
13  The Renesas RZ/T2H and RZ/N2H SoCs feature a combined Pin and GPIO controller.
14  Pin multiplexing and GPIO configuration are performed on a per-pin basis.
15  Each port supports up to 8 pins, each configurable for either GPIO (port mode)
16  or alternate function mode. Each pin supports function mode values ranging from
17  0x0 to 0x2A, allowing selection from up to 43 different functions.
18
19properties:
20  compatible:
21    enum:
22      - renesas,r9a09g077-pinctrl # RZ/T2H
23      - renesas,r9a09g087-pinctrl # RZ/N2H
24
25  reg:
26    minItems: 1
27    items:
28      - description: Non-safety I/O Port base
29      - description: Safety I/O Port safety region base
30      - description: Safety I/O Port Non-safety region base
31
32  reg-names:
33    minItems: 1
34    items:
35      - const: nsr
36      - const: srs
37      - const: srn
38
39  gpio-controller: true
40
41  '#gpio-cells':
42    const: 2
43    description:
44      The first cell contains the global GPIO port index, constructed using the
45      RZT2H_GPIO() helper macro from <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>
46      (e.g. "RZT2H_GPIO(3, 0)" for P03_0). The second cell represents the consumer
47      flag. Use the macros defined in include/dt-bindings/gpio/gpio.h.
48
49  gpio-ranges:
50    maxItems: 1
51
52  clocks:
53    maxItems: 1
54
55  power-domains:
56    maxItems: 1
57
58definitions:
59  renesas-rzt2h-n2h-pins-node:
60    type: object
61    allOf:
62      - $ref: pincfg-node.yaml#
63      - $ref: pinmux-node.yaml#
64    properties:
65      pinmux:
66        description:
67          Values are constructed from I/O port number, pin number, and
68          alternate function configuration number using the RZT2H_PORT_PINMUX()
69          helper macro from <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>.
70      pins: true
71      phandle: true
72      input: true
73      input-enable: true
74      output-enable: true
75    oneOf:
76      - required: [pinmux]
77      - required: [pins]
78    additionalProperties: false
79
80patternProperties:
81  # Grouping nodes: allow multiple "-pins" subnodes within a "-group"
82  '.*-group$':
83    type: object
84    description:
85      Pin controller client devices can organize pin configuration entries into
86      grouping nodes ending in "-group". These group nodes may contain multiple
87      child nodes each ending in "-pins" to configure distinct sets of pins.
88    additionalProperties: false
89    patternProperties:
90      '-pins$':
91        $ref: '#/definitions/renesas-rzt2h-n2h-pins-node'
92
93  # Standalone "-pins" nodes under client devices or groups
94  '-pins$':
95    $ref: '#/definitions/renesas-rzt2h-n2h-pins-node'
96
97  '-hog$':
98    type: object
99    description: GPIO hog node
100    properties:
101      gpio-hog: true
102      gpios: true
103      input: true
104      output-high: true
105      output-low: true
106      line-name: true
107    required:
108      - gpio-hog
109      - gpios
110    additionalProperties: false
111
112allOf:
113  - $ref: pinctrl.yaml#
114
115required:
116  - compatible
117  - reg
118  - reg-names
119  - gpio-controller
120  - '#gpio-cells'
121  - gpio-ranges
122  - clocks
123  - power-domains
124
125unevaluatedProperties: false
126
127examples:
128  - |
129    #include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>
130    #include <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>
131
132    pinctrl@802c0000 {
133        compatible = "renesas,r9a09g077-pinctrl";
134        reg = <0x802c0000 0x2000>,
135              <0x812c0000 0x2000>,
136              <0x802b0000 0x2000>;
137        reg-names = "nsr", "srs", "srn";
138        clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
139        gpio-controller;
140        #gpio-cells = <2>;
141        gpio-ranges = <&pinctrl 0 0 288>;
142        power-domains = <&cpg>;
143
144        serial0-pins {
145            pinmux = <RZT2H_PORT_PINMUX(38, 0, 1)>, /* Tx */
146                     <RZT2H_PORT_PINMUX(38, 1, 1)>; /* Rx */
147        };
148
149        sd1-pwr-en-hog {
150            gpio-hog;
151            gpios = <RZT2H_GPIO(39, 2) 0>;
152            output-high;
153            line-name = "sd1_pwr_en";
154        };
155
156        i2c0-pins {
157            pins = "RIIC0_SDA", "RIIC0_SCL";
158            input-enable;
159        };
160
161        sd0-sd-group {
162            ctrl-pins {
163                pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>, /* SD0_CLK */
164                         <RZT2H_PORT_PINMUX(12, 1, 0x29)>; /* SD0_CMD */
165            };
166
167            data-pins {
168                pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>, /* SD0_CLK */
169                         <RZT2H_PORT_PINMUX(12, 1, 0x29)>; /* SD0_CMD */
170            };
171        };
172    };
173