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/linux/drivers/gpu/drm/xe/
H A Dxe_ggtt.c1 // SPDX-License-Identifier: MIT
9 #include <linux/fault-inject.h>
10 #include <linux/io-64-nonatomic-lo-hi.h>
41 * for resources that are accessible to privileged (i.e. kernel-mode) processes,
42 * and not tied to a specific user-level process. For example, the Graphics
43 * micro-Controller (GuC) and Display Engine (if present) utilize this Global
47 * address that can be accessed by HW. The GGTT is a flat, single-level table.
62 * GGTT. These simplifications might waste space in the GGTT (about 20-25 MBs
109 struct xe_tile *tile = ggtt->tile; in ggtt_update_access_counter() local
113 if (tile->primary_gt && XE_GT_WA(tile->primary_gt, 22019338487)) { in ggtt_update_access_counter()
[all …]
H A Dxe_gt_sriov_pf_config.c1 // SPDX-License-Identifier: MIT
3 * Copyright © 2023-2024 Intel Corporation
57 return xe_guc_ct_send_block(&guc->ct, request, ARRAY_SIZE(request)); in guc_action_update_vf_cfg()
65 struct xe_guc *guc = &gt->uc.guc; in pf_send_vf_cfg_reset()
70 return ret <= 0 ? ret : -EPROTO; in pf_send_vf_cfg_reset()
79 struct xe_guc *guc = &gt->uc.guc; in pf_send_vf_buf_klvs()
85 * Return: 0 on success, -ENOKEY if some KLVs were not updated, -EPROTO if reply was malformed,
96 int err = ret < 0 ? ret : ret < num_klvs ? -ENOKEY : -EPROTO; in pf_push_vf_buf_klvs()
98 struct drm_printer p = xe_gt_info_printer(gt); in pf_push_vf_buf_klvs() local
104 xe_guc_klv_print(klvs, num_dwords, &p); in pf_push_vf_buf_klvs()
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H A Dxe_guc.c1 // SPDX-License-Identifier: MIT
57 * For most BOs, the address on the allocating tile is fine. However for in guc_bo_ggtt_addr()
58 * some, e.g. G2G CTB, the address on a specific tile is required as it in guc_bo_ggtt_addr()
59 * might be different for each tile. So, just always ask for the address in guc_bo_ggtt_addr()
62 addr = __xe_bo_ggtt_addr(bo, gt_to_tile(guc_to_gt(guc))->id); in guc_bo_ggtt_addr()
67 xe_assert(xe, xe_bo_size(bo) <= GUC_GGTT_TOP - addr); in guc_bo_ggtt_addr()
74 u32 level = xe_guc_log_get_level(&guc->log); in guc_ctl_debug_flags()
90 if (!xe->info.skip_guc_pc) in guc_ctl_feature_flags()
93 if (xe_configfs_get_psmi_enabled(to_pci_dev(xe->dr in guc_ctl_feature_flags()
460 struct xe_tile *tile = gt_to_tile(gt); guc_g2g_alloc() local
555 u32 tile, dev; guc_g2g_start() local
684 struct xe_tile *tile = gt_to_tile(guc_to_gt(guc)); xe_guc_realloc_post_hwconfig() local
1343 struct xe_tile *tile = gt_to_tile(gt); xe_guc_enable_communication() local
1635 xe_guc_print_info(struct xe_guc * guc,struct drm_printer * p) xe_guc_print_info() argument
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H A Dxe_pci.c1 // SPDX-License-Identifier: MIT
45 __diag_ignore_all("-Woverride-init", "Allow field overrides in table");
129 /* Pre-GMDID Graphics IPs */
135 /* GMDID-based Graphics IPs */
151 /* Pre-GMDID Media IPs */
155 /* GMDID-based Media IPs */
453 char *s, *p, *tok; in device_id_in_list() local
469 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) { in device_id_in_list()
505 for (sp = desc->subplatforms; sp && sp->subplatform; sp++) in find_subplatform()
506 for (id = sp->pciidlist; *id; id++) in find_subplatform()
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H A Dxe_svm.c1 // SPDX-License-Identifier: MIT
31 .__flags = READ_ONCE(range->base.pages.flags.__flags), in xe_svm_range_in_vram()
40 return xe_svm_range_in_vram(range) && range->tile_present; in xe_svm_range_has_vram_binding()
50 return gpusvm_to_vm(r->gpusvm); in range_to_vm()
54 vm_dbg(&range_to_vm(&(r__)->base)->xe->drm, \
55 "%s: asid=%u, gpusvm=%p, vram=%d,%d, seqno=%lu, " \
57 (operation__), range_to_vm(&(r__)->base)->usm.asid, \
58 (r__)->base.gpusvm, \
61 (r__)->base.pages.notifier_seq, \
79 INIT_LIST_HEAD(&range->garbage_collector_link); in xe_svm_range_alloc()
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H A Dxe_huc.c1 // SPDX-License-Identifier: MIT
43 return &container_of(huc, struct xe_uc, huc)->guc; in huc_to_guc()
61 huc->gsc_pkt = bo; in huc_alloc_gsc_pkt()
72 huc->fw.type = XE_UC_FW_TYPE_HUC; in xe_huc_init()
81 xe_uc_fw_change_status(&huc->fw, XE_UC_FIRMWARE_NOT_SUPPORTED); in xe_huc_init()
85 ret = xe_uc_fw_init(&huc->fw); in xe_huc_init()
89 if (!xe_uc_fw_is_enabled(&huc->fw)) in xe_huc_init()
95 if (huc->fw.has_gsc_headers) { in xe_huc_init()
101 xe_uc_fw_change_status(&huc->f in xe_huc_init()
69 struct xe_tile *tile = gt_to_tile(gt); xe_huc_init() local
108 struct xe_tile *tile = gt_to_tile(huc_to_gt(huc)); xe_huc_init_post_hwconfig() local
296 xe_huc_print_info(struct xe_huc * huc,struct drm_printer * p) xe_huc_print_info() argument
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H A Dxe_vm.c1 // SPDX-License-Identifier: MIT
8 #include <linux/dma-fence-array.h>
47 return vm->gpuvm.r_obj; in xe_vm_obj()
51 * xe_vm_drm_exec_lock() - Lock the vm's resv with a drm_exec transaction
68 lockdep_assert_held(&vm->lock); in preempt_fences_waiting()
71 list_for_each_entry(q, &vm->preempt.exec_queues, lr.link) { in preempt_fences_waiting()
72 if (!q->lr.pfence || in preempt_fences_waiting()
74 &q->lr.pfence->flags)) { in preempt_fences_waiting()
93 lockdep_assert_held(&vm->lock); in alloc_preempt_fences()
96 if (*count >= vm->preempt.num_exec_queues) in alloc_preempt_fences()
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H A Dxe_gt.c1 // SPDX-License-Identifier: MIT
68 struct xe_gt *xe_gt_alloc(struct xe_tile *tile) in xe_gt_alloc() argument
70 struct xe_device *xe = tile_to_xe(tile); in xe_gt_alloc()
71 struct drm_device *drm = &xe->drm; in xe_gt_alloc()
72 bool shared_wq = xe->info.needs_shared_vf_gt_wq && tile->primary_gt && in xe_gt_alloc()
79 return ERR_PTR(-ENOMEM); in xe_gt_alloc()
81 gt->tile = tile; in xe_gt_alloc()
82 if (shared_wq && tile->primary_gt->ordered_wq) in xe_gt_alloc()
83 ordered_wq = tile->primary_gt->ordered_wq; in xe_gt_alloc()
85 ordered_wq = drmm_alloc_ordered_workqueue(drm, "gt-ordered-wq", in xe_gt_alloc()
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H A Dxe_guc_hwconfig.c1 // SPDX-License-Identifier: MIT
43 int ret = send_get_hwconfig(guc, xe_bo_ggtt_addr(guc->hwconfig.bo), in guc_hwconfig_copy()
44 guc->hwconfig.size); in guc_hwconfig_copy()
56 struct xe_tile *tile = gt_to_tile(gt); in xe_guc_hwconfig_init() local
62 if (guc->hwconfig.bo) in xe_guc_hwconfig_init()
68 if (gt->info.id != XE_GT0) in xe_guc_hwconfig_init()
72 if (GRAPHICS_VERx100(xe) < 1255 && xe->info.platform != XE_ALDERLAKE_P) in xe_guc_hwconfig_init()
79 return -EINVAL; in xe_guc_hwconfig_init()
81 bo = xe_managed_bo_create_pin_map(xe, tile, PAGE_ALIGN(size), in xe_guc_hwconfig_init()
87 guc->hwconfig.bo = bo; in xe_guc_hwconfig_init()
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H A Dxe_device.c1 // SPDX-License-Identifier: MIT
10 #include <linux/fault-inject.h>
85 int ret = -ENOMEM; in xe_file_open()
98 xef->drm = file; in xe_file_open()
99 xef->client = client; in xe_file_open()
100 xef->xe = xe; in xe_file_open()
102 mutex_init(&xef->vm.lock); in xe_file_open()
103 xa_init_flags(&xef->vm.xa, XA_FLAGS_ALLOC1); in xe_file_open()
105 mutex_init(&xef->exec_queue.lock); in xe_file_open()
106 xa_init_flags(&xef->exec_queue.xa, XA_FLAGS_ALLOC1); in xe_file_open()
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H A Dxe_vm.h1 /* SPDX-License-Identifier: MIT */
36 drm_gpuvm_get(&vm->gpuvm); in xe_vm_get()
42 drm_gpuvm_put(&vm->gpuvm); in xe_vm_put()
51 /* Only guaranteed not to change when vm->lock is held */ in xe_vm_is_closed()
52 return !vm->size; in xe_vm_is_closed()
57 return vm->flags & XE_VM_FLAG_BANNED; in xe_vm_is_banned()
62 lockdep_assert_held(&vm->lock); in xe_vm_is_closed_or_banned()
72 * xe_vm_has_scratch() - Whether the vm is configured for scratch PTEs
79 return vm->flags & XE_VM_FLAG_SCRATCH_PAGE; in xe_vm_has_scratch()
83 * gpuvm_to_vm() - Return the embedding xe_vm from a struct drm_gpuvm pointer
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H A Dxe_wa.c1 // SPDX-License-Identifier: MIT
11 #include <linux/fault-inject.h>
37 * - LRC workarounds: workarounds that touch registers that are
45 * - Engine workarounds: the list of these WAs is applied whenever the specific
57 * - GT workarounds: the list of these WAs is applied whenever these registers
60 * - Register whitelist: some workarounds need to be implemented in userspace,
64 * these to/be-whitelisted registers to some special HW registers).
66 * - Workaround batchbuffers: buffers that get executed automatically by the
88 * |-
1042 unsigned long *p; xe_wa_device_init() local
1066 unsigned long *p; xe_wa_gt_init() local
1090 xe_wa_device_dump(struct xe_device * xe,struct drm_printer * p) xe_wa_device_dump() argument
1100 xe_wa_dump(struct xe_gt * gt,struct drm_printer * p) xe_wa_dump() argument
1134 xe_wa_apply_tile_workarounds(struct xe_tile * tile) xe_wa_apply_tile_workarounds() argument
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H A Dxe_guc_log.c1 // SPDX-License-Identifier: MIT
8 #include <linux/fault-inject.h>
47 * +-------------------------------+ 32B in guc_log_size()
49 * +-------------------------------+ 64B in guc_log_size()
51 * +-------------------------------+ 96B in guc_log_size()
82 snapshot->size = xe_bo_size(log->bo); in xe_guc_log_snapshot_alloc()
83 snapshot->num_chunks = DIV_ROUND_UP(snapshot->size, GUC_LOG_CHUNK_SIZE); in xe_guc_log_snapshot_alloc()
85 snapshot->copy = kcalloc(snapshot->num_chunks, sizeof(*snapshot->copy), in xe_guc_log_snapshot_alloc()
87 if (!snapshot->copy) in xe_guc_log_snapshot_alloc()
90 remain = snapshot->size; in xe_guc_log_snapshot_alloc()
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/linux/drivers/gpu/drm/xe/tests/
H A Dxe_guc_buf_kunit.c1 // SPDX-License-Identifier: GPL-2.0 AND MIT
8 #include <kunit/test-bug.h>
20 struct xe_tile *tile, in replacement_xe_managed_bo_create_pin_map() argument
27 bo = drmm_kzalloc(&xe->drm, sizeof(*bo), GFP_KERNEL); in replacement_xe_managed_bo_create_pin_map()
30 buf = drmm_kzalloc(&xe->drm, size, GFP_KERNEL); in replacement_xe_managed_bo_create_pin_map()
33 bo->tile = tile; in replacement_xe_managed_bo_create_pin_map()
34 bo->ttm.bdev = &xe->ttm; in replacement_xe_managed_bo_create_pin_map()
35 bo->ttm.base.size = size; in replacement_xe_managed_bo_create_pin_map()
36 iosys_map_set_vaddr(&bo->vmap, buf); in replacement_xe_managed_bo_create_pin_map()
39 struct xe_ggtt *ggtt = tile->mem.ggtt; in replacement_xe_managed_bo_create_pin_map()
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/linux/drivers/hid/
H A Dhid-picolcd_fb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2010-2012 by Bruno Prémont <bonbons@linux-vserver.org> *
16 #include "hid-picolcd.h"
22 * each. Each tile has 8x64 pixel, each data byte representing
23 * a 1-bit wide vertical line of the tile.
25 * The display can be updated at a tile granularity.
28 * +----------------+----------------+----------------+----------------+
29 * | Tile 1 | Tile 1 | Tile 1 | Tile 1 |
30 * +----------------+----------------+----------------+----------------+
31 * | Tile 2 | Tile 2 | Tile 2 | Tile 2 |
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/linux/drivers/media/platform/verisilicon/
H A Dhantro_hw.h1 /* SPDX-License-Identifier: GPL-2.0 */
13 #include <linux/v4l2-controls.h>
14 #include <media/v4l2-ctrls.h>
15 #include <media/v4l2-vp9.h>
16 #include <media/videobuf2-core.h>
58 * struct hantro_aux_buf - auxiliary DMA buffer for hardware data
93 * @p: P reflis
98 struct v4l2_h264_reference p[V4L2_H264_REF_LIST_LEN]; global() member
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/linux/drivers/gpu/drm/nouveau/
H A Dnouveau_bo.c30 #include <linux/dma-mapping.h>
52 * NV10-NV40 tiling helpers
60 int i = reg - drm->tile.reg; in nv10_bo_update_tile_region()
62 struct nvkm_fb_tile *tile = &fb->tile.region[i]; in nv10_bo_update_tile_region() local
64 nouveau_fence_unref(&reg->fence); in nv10_bo_update_tile_region()
66 if (tile->pitch) in nv10_bo_update_tile_region()
67 nvkm_fb_tile_fini(fb, i, tile); in nv10_bo_update_tile_region()
70 nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile); in nv10_bo_update_tile_region()
72 nvkm_fb_tile_prog(fb, i, tile); in nv10_bo_update_tile_region()
79 struct nouveau_drm_tile *tile = &drm->tile.reg[i]; in nv10_bo_get_tile_region() local
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/linux/drivers/media/platform/mediatek/vcodec/decoder/vdec/
H A Dvdec_av1_req_lat_if.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <media/videobuf2-dma-contig.h>
22 #define AV1_REF_INVALID_SCALE -1
26 #define AV1_INVALID_IDX -1
39 (((_value_) < 0) ? -AV1_DIV_ROUND_UP_POW2(-(_value_), (_n_)) \
43 #define BIT_FLAG(x, bit) (!!((x)->flag
490 struct vdec_av1_slice_tile tile; global() member
662 struct vdec_av1_slice_mem tile; global() member
718 struct mtk_vcodec_mem tile; global() member
1292 struct vdec_av1_slice_tile *tile = &frame->uh.tile; vdec_av1_slice_setup_tile() local
1393 struct vdec_av1_slice_tile *tile = &uh->tile; vdec_av1_slice_setup_tile_group() local
1662 struct vdec_av1_slice_tile *tile = &uh->tile; vdec_av1_slice_setup_tile_buffer() local
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/linux/Documentation/userspace-api/media/v4l/
H A Dext-ctrls-codec-stateless.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
4 .. _codec-stateless-controls:
19 .. _codec-stateless-control-id:
24 .. _v4l2-codec-stateless-h264:
42 .. tabularcolumns:: |p{1.2cm}|p{8.6cm}|p{7.5cm}|
44 .. flat-table:: struct v4l2_ctrl_h264_sps
45 :header-rows: 0
46 :stub-columns: 0
49 * - __u8
50 - ``profile_idc``
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/linux/include/linux/
H A Dfb.h1 /* SPDX-License-Identifier: GPL-2.0 */
77 __u32 serial; /* Serial Number - Integer */
84 __u16 input; /* display type - see FB_DISP_* */
85 __u16 dpms; /* DPMS support - see FB_DPMS_ */
86 __u16 signal; /* Signal Type - see FB_SIGNAL_* */
89 __u16 gamma; /* Gamma - in fractions of 100 */
91 __u16 misc; /* Misc flags - see FB_MISC_* */
133 /* only used by mach-pxa/am200epd.c */
197 /* Format: test_bit(width - 1, blit_x) */
198 /* test_bit(height - 1, blit_y) */
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/linux/include/uapi/drm/
H A Ddrm_fourcc.h39 * further describe the buffer's format - for example tiling or compression.
42 * ----------------
56 * vendor-namespaced, and as such the relationship between a fourcc code and a
58 * may preserve meaning - such as number of planes - from the fourcc code,
64 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
76 * - Kernel and user-space drivers: for drivers it's important that modifiers
80 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
93 * -----------------------
98 * upstream in-kernel or open source userspace user does not apply.
225 * Half-Floating point - 16b/component
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/linux/tools/include/asm/
H A Dbarrier.h1 /* SPDX-License-Identifier: GPL-2.0 */
20 #include "../../arch/tile/include/asm/barrier.h"
30 #include <asm-generic/barrier.h>
51 # define smp_store_release(p, v) \ argument
54 WRITE_ONCE(*p, v); \
59 # define smp_load_acquire(p) \ argument
61 typeof(*p) ___p1 = READ_ONCE(*p); \
/linux/drivers/video/fbdev/
H A Dgbefb.c4 * Copyright (C) 1999 Silicon Graphics, Inc. - Jeffrey Newquist
5 * Copyright (C) 2002 Vivien Chappelier <vivien.chappelier@linux-mips.org>
14 #include <linux/dma-mapping.h>
15 #include <linux/dma-direct.h>
45 /* macro for fastest write-though access to the framebuffer */
64 #define TILE_MASK (TILE_SIZE - 1)
88 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
103 .height = -1,
104 .width = -1,
134 .height = -1,
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/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dpriv.h1 /* SPDX-License-Identifier: MIT */
4 #define nvkm_gr(p) container_of((p), struct nvkm_gr, engine) argument
23 void (*tile)(struct nvkm_gr *, int region, struct nvkm_fb_tile *); member
28 /* Returns chipset-specific counts of units packed into an u64.
/linux/drivers/gpu/drm/nouveau/include/nvkm/core/
H A Dengine.h1 /* SPDX-License-Identifier: MIT */
4 #define nvkm_engine(p) container_of((p), struct nvkm_engine, subdev) argument
27 void (*tile)(struct nvkm_engine *, int region, struct nvkm_fb_tile *); member

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