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/linux/drivers/gpu/drm/xe/tests/
H A Dxe_guc_buf_kunit.c1 // SPDX-License-Identifier: GPL-2.0 AND MIT
8 #include <kunit/test-bug.h>
20 struct xe_tile *tile, in replacement_xe_managed_bo_create_pin_map() argument
27 bo = drmm_kzalloc(&xe->drm, sizeof(*bo), GFP_KERNEL); in replacement_xe_managed_bo_create_pin_map()
30 buf = drmm_kzalloc(&xe->drm, size, GFP_KERNEL); in replacement_xe_managed_bo_create_pin_map()
33 bo->tile = tile; in replacement_xe_managed_bo_create_pin_map()
34 bo->ttm.bdev = &xe->ttm; in replacement_xe_managed_bo_create_pin_map()
35 bo->ttm.base.size = size; in replacement_xe_managed_bo_create_pin_map()
36 iosys_map_set_vaddr(&bo->vmap, buf); in replacement_xe_managed_bo_create_pin_map()
39 struct xe_ggtt *ggtt = tile->mem.ggtt; in replacement_xe_managed_bo_create_pin_map()
[all …]
/linux/drivers/hid/
H A Dhid-picolcd_fb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2010-2012 by Bruno Prémont <bonbons@linux-vserver.org> *
16 #include "hid-picolcd.h"
22 * each. Each tile has 8x64 pixel, each data byte representing
23 * a 1-bit wide vertical line of the tile.
25 * The display can be updated at a tile granularity.
28 * +----------------+----------------+----------------+----------------+
29 * | Tile 1 | Tile 1 | Tile 1 | Tile 1 |
30 * +----------------+----------------+----------------+----------------+
31 * | Tile 2 | Tile 2 | Tile 2 | Tile 2 |
[all …]
/linux/drivers/media/platform/verisilicon/
H A Dhantro_hw.h1 /* SPDX-License-Identifier: GPL-2.0 */
13 #include <linux/v4l2-controls.h>
14 #include <media/v4l2-ctrls.h>
15 #include <media/v4l2-vp9.h>
16 #include <media/videobuf2-core.h>
58 * struct hantro_aux_buf - auxiliary DMA buffer for hardware data
93 * @p: P reflist
98 struct v4l2_h264_reference p[V4L2_H264_REF_LIST_LEN]; member
108 * @reflists: P/B0/B1 reflists
110 * @dpb_longterm: DPB long-term
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/linux/drivers/gpu/drm/xe/
H A Dxe_gt_sriov_pf_config.c1 // SPDX-License-Identifier: MIT
3 * Copyright © 2023-2024 Intel Corporation
56 return xe_guc_ct_send_block(&guc->ct, request, ARRAY_SIZE(request)); in guc_action_update_vf_cfg()
64 struct xe_guc *guc = &gt->uc.guc; in pf_send_vf_cfg_reset()
69 return ret <= 0 ? ret : -EPROTO; in pf_send_vf_cfg_reset()
78 struct xe_guc *guc = &gt->uc.guc; in pf_send_vf_buf_klvs()
84 * Return: 0 on success, -ENOKEY if some KLVs were not updated, -EPROTO if reply was malformed,
95 int err = ret < 0 ? ret : ret < num_klvs ? -ENOKEY : -EPROTO; in pf_push_vf_buf_klvs()
97 struct drm_printer p = xe_gt_info_printer(gt); in pf_push_vf_buf_klvs() local
103 xe_guc_klv_print(klvs, num_dwords, &p); in pf_push_vf_buf_klvs()
[all …]
H A Dxe_guc.c1 // SPDX-License-Identifier: MIT
54 * For most BOs, the address on the allocating tile is fine. However for in guc_bo_ggtt_addr()
55 * some, e.g. G2G CTB, the address on a specific tile is required as it in guc_bo_ggtt_addr()
56 * might be different for each tile. So, just always ask for the address in guc_bo_ggtt_addr()
59 addr = __xe_bo_ggtt_addr(bo, gt_to_tile(guc_to_gt(guc))->id); in guc_bo_ggtt_addr()
64 xe_assert(xe, xe_bo_size(bo) <= GUC_GGTT_TOP - addr); in guc_bo_ggtt_addr()
71 u32 level = xe_guc_log_get_level(&guc->log); in guc_ctl_debug_flags()
87 if (!xe->info.skip_guc_pc) in guc_ctl_feature_flags()
90 if (xe_configfs_get_psmi_enabled(to_pci_dev(xe->drm.dev))) in guc_ctl_feature_flags()
98 u32 offset = guc_bo_ggtt_addr(guc, guc->log.bo) >> PAGE_SHIFT; in guc_ctl_log_params_flags()
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H A Dxe_huc.c1 // SPDX-License-Identifier: MIT
43 return &container_of(huc, struct xe_uc, huc)->guc; in huc_to_guc()
61 huc->gsc_pkt = bo; in huc_alloc_gsc_pkt()
69 struct xe_tile *tile = gt_to_tile(gt); in xe_huc_init() local
73 huc->fw.type = XE_UC_FW_TYPE_HUC; in xe_huc_init()
76 if (tile->media_gt && (gt != tile->media_gt)) { in xe_huc_init()
77 xe_uc_fw_change_status(&huc->fw, XE_UC_FIRMWARE_NOT_SUPPORTED); in xe_huc_init()
81 ret = xe_uc_fw_init(&huc->fw); in xe_huc_init()
85 if (!xe_uc_fw_is_enabled(&huc->fw)) in xe_huc_init()
91 if (huc->fw.has_gsc_headers) { in xe_huc_init()
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H A Dxe_guc_hwconfig.c1 // SPDX-License-Identifier: MIT
43 int ret = send_get_hwconfig(guc, xe_bo_ggtt_addr(guc->hwconfig.bo), in guc_hwconfig_copy()
44 guc->hwconfig.size); in guc_hwconfig_copy()
56 struct xe_tile *tile = gt_to_tile(gt); in xe_guc_hwconfig_init() local
62 if (guc->hwconfig.bo) in xe_guc_hwconfig_init()
68 if (gt->info.id != XE_GT0) in xe_guc_hwconfig_init()
72 if (GRAPHICS_VERx100(xe) < 1255 && xe->info.platform != XE_ALDERLAKE_P) in xe_guc_hwconfig_init()
79 return -EINVAL; in xe_guc_hwconfig_init()
81 bo = xe_managed_bo_create_pin_map(xe, tile, PAGE_ALIGN(size), in xe_guc_hwconfig_init()
87 guc->hwconfig.bo = bo; in xe_guc_hwconfig_init()
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H A Dxe_gt.c1 // SPDX-License-Identifier: MIT
72 destroy_workqueue(gt->ordered_wq); in gt_fini()
75 struct xe_gt *xe_gt_alloc(struct xe_tile *tile) in xe_gt_alloc() argument
80 gt = drmm_kzalloc(&tile_to_xe(tile)->drm, sizeof(*gt), GFP_KERNEL); in xe_gt_alloc()
82 return ERR_PTR(-ENOMEM); in xe_gt_alloc()
84 gt->tile = tile; in xe_gt_alloc()
85 gt->ordered_wq = alloc_ordered_workqueue("gt-ordered-wq", in xe_gt_alloc()
88 err = drmm_add_action_or_reset(&gt_to_xe(gt)->drm, gt_fini, gt); in xe_gt_alloc()
101 xe_guc_submit_disable(&gt->uc.guc); in xe_gt_sanitize()
162 fence = dma_fence_get(&job->drm.s_fence->finished); in emit_job_sync()
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H A Dxe_vm.h1 /* SPDX-License-Identifier: MIT */
36 drm_gpuvm_get(&vm->gpuvm); in xe_vm_get()
42 drm_gpuvm_put(&vm->gpuvm); in xe_vm_put()
51 /* Only guaranteed not to change when vm->lock is held */ in xe_vm_is_closed()
52 return !vm->size; in xe_vm_is_closed()
57 return vm->flags & XE_VM_FLAG_BANNED; in xe_vm_is_banned()
62 lockdep_assert_held(&vm->lock); in xe_vm_is_closed_or_banned()
72 * xe_vm_has_scratch() - Whether the vm is configured for scratch PTEs
79 return vm->flags & XE_VM_FLAG_SCRATCH_PAGE; in xe_vm_has_scratch()
83 * gpuvm_to_vm() - Return the embedding xe_vm from a struct drm_gpuvm pointer
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H A Dxe_guc_log.c1 // SPDX-License-Identifier: MIT
8 #include <linux/fault-inject.h>
47 * +-------------------------------+ 32B in guc_log_size()
49 * +-------------------------------+ 64B in guc_log_size()
51 * +-------------------------------+ 96B in guc_log_size()
82 snapshot->size = xe_bo_size(log->bo); in xe_guc_log_snapshot_alloc()
83 snapshot->num_chunks = DIV_ROUND_UP(snapshot->size, GUC_LOG_CHUNK_SIZE); in xe_guc_log_snapshot_alloc()
85 snapshot->copy = kcalloc(snapshot->num_chunks, sizeof(*snapshot->copy), in xe_guc_log_snapshot_alloc()
87 if (!snapshot->copy) in xe_guc_log_snapshot_alloc()
90 remain = snapshot->size; in xe_guc_log_snapshot_alloc()
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H A Dxe_configfs.c1 // SPDX-License-Identifier: MIT
28 * Configfs is a filesystem-based manager of kernel objects. XE KMD registers a
73 * -------------------
83 * ----------------
87 * considered on each tile. Examples:
97 * Note that the engine names are the per-GT hardware names. On multi-tile
99 * and copy engines on each tile.
109 * ----
121 * ------------------
134 * <engine-class> cmd <instr> [[dword0] [dword1] [...]]
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/linux/drivers/gpu/drm/nouveau/
H A Dnouveau_bo.c30 #include <linux/dma-mapping.h>
52 * NV10-NV40 tiling helpers
60 int i = reg - drm->tile.reg; in nv10_bo_update_tile_region()
62 struct nvkm_fb_tile *tile = &fb->tile.region[i]; in nv10_bo_update_tile_region() local
64 nouveau_fence_unref(&reg->fence); in nv10_bo_update_tile_region()
66 if (tile->pitch) in nv10_bo_update_tile_region()
67 nvkm_fb_tile_fini(fb, i, tile); in nv10_bo_update_tile_region()
70 nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile); in nv10_bo_update_tile_region()
72 nvkm_fb_tile_prog(fb, i, tile); in nv10_bo_update_tile_region()
79 struct nouveau_drm_tile *tile = &drm->tile.reg[i]; in nv10_bo_get_tile_region() local
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/linux/drivers/media/platform/mediatek/vcodec/decoder/vdec/
H A Dvdec_av1_req_lat_if.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <media/videobuf2-dma-contig.h>
22 #define AV1_REF_INVALID_SCALE -1
26 #define AV1_INVALID_IDX -1
39 (((_value_) < 0) ? -AV1_DIV_ROUND_UP_POW2(-(_value_), (_n_)) \
43 #define BIT_FLAG(x, bit) (!!((x)->flags & (bit)))
44 #define SEGMENTATION_FLAG(x, name) (!!((x)->flags & V4L2_AV1_SEGMENTATION_FLAG_##name))
45 #define QUANT_FLAG(x, name) (!!((x)->flags & V4L2_AV1_QUANTIZATION_FLAG_##name))
46 #define SEQUENCE_FLAG(x, name) (!!((x)->flags & V4L2_AV1_SEQUENCE_FLAG_##name))
47 #define FH_FLAG(x, name) (!!((x)->flags & V4L2_AV1_FRAME_FLAG_##name))
[all …]
H A Dvdec_vp9_req_lat_if.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <media/videobuf2-dma-contig.h>
10 #include <media/v4l2-vp9.h>
28 #define HDR_FLAG(x) (!!((hdr)->flags & V4L2_VP9_FRAME_FLAG_##x))
29 #define LF_FLAG(x) (!!((lf)->flags & V4L2_VP9_LOOP_FILTER_FLAG_##x))
30 #define SEG_FLAG(x) (!!((seg)->flags & V4L2_VP9_SEGMENTATION_FLAG_##x))
34 * struct vdec_vp9_slice_frame_ctx - vp9 prob tables footprint
85 * struct vdec_vp9_slice_frame_counts - vp9 counts tables footprint
139 * struct vdec_vp9_slice_counts_map - vp9 counts tables to map
168 * struct vdec_vp9_slice_uncompressed_header - vp9 uncompressed header syntax
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/linux/Documentation/userspace-api/media/v4l/
H A Dext-ctrls-codec-stateless.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _codec-stateless-controls:
18 .. _codec-stateless-control-id:
23 .. _v4l2-codec-stateless-h264:
41 .. tabularcolumns:: |p{1.2cm}|p{8.6cm}|p{7.5cm}|
43 .. flat-table:: struct v4l2_ctrl_h264_sps
44 :header-rows: 0
45 :stub-columns: 0
48 * - __u8
49 - ``profile_idc``
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H A Dpixfmt-reserved.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _pixfmt-reserved:
11 register your own format, send an e-mail to the linux-media mailing list
15 copy to the linux-media mailing list for inclusion in this section. If
17 please make a proposal on the linux-media mailing list.
20 .. tabularcolumns:: |p{6.6cm}|p{2.2cm}|p{8.5cm}|
26 .. _reserved-formats:
28 .. flat-table:: Reserved Image Formats
29 :header-rows: 1
30 :stub-columns: 0
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/linux/include/linux/
H A Dfb.h1 /* SPDX-License-Identifier: GPL-2.0 */
77 __u32 serial; /* Serial Number - Integer */
84 __u16 input; /* display type - see FB_DISP_* */
85 __u16 dpms; /* DPMS support - see FB_DPMS_ */
86 __u16 signal; /* Signal Type - see FB_SIGNAL_* */
89 __u16 gamma; /* Gamma - in fractions of 100 */
91 __u16 misc; /* Misc flags - see FB_MISC_* */
133 /* only used by mach-pxa/am200epd.c */
197 /* Format: test_bit(width - 1, blit_x) */
198 /* test_bit(height - 1, blit_y) */
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/linux/include/uapi/drm/
H A Ddrm_fourcc.h39 * further describe the buffer's format - for example tiling or compression.
42 * ---------
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/linux/tools/include/asm/
H A Dbarrier.h1 /* SPDX-License-Identifier: GPL-2.0 */
20 #include "../../arch/tile/include/asm/barrier.h"
30 #include <asm-generic/barrier.h>
51 # define smp_store_release(p, v) \ argument
54 WRITE_ONCE(*p, v); \
59 # define smp_load_acquire(p) \ argument
61 typeof(*p) ___p1 = READ_ONCE(*p); \
/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dpriv.h1 /* SPDX-License-Identifier: MIT */
4 #define nvkm_gr(p) container_of((p), struct nvkm_gr, engine) argument
23 void (*tile)(struct nvkm_gr *, int region, struct nvkm_fb_tile *); member
28 /* Returns chipset-specific counts of units packed into an u64.
H A Dnv10.c216 NV10_PGRAPH_WINDOWCLIP_HORIZONTAL, /* 8 values from 0x400f00-0x400f1c */
217 NV10_PGRAPH_WINDOWCLIP_VERTICAL, /* 8 values from 0x400f20-0x400f3c */
389 #define nv10_gr(p) container_of((p), struct nv10_gr, base) argument
397 #define nv10_gr_chan(p) container_of((p), struct nv10_gr_chan, object) argument
433 struct nvkm_device *device = chan->object.engine->subdev.device; in nv17_gr_mthd_lma_window()
434 struct nvkm_gr *gr = &chan->gr->base; in nv17_gr_mthd_lma_window()
435 struct pipe_state *pipe = &chan->pipe_state; in nv17_gr_mthd_lma_window()
440 chan->lma_window[(mthd - 0x1638) / 4] = data; in nv17_gr_mthd_lma_window()
448 PIPE_SAVE(device, pipe->pipe_0x0200, 0x0200); in nv17_gr_mthd_lma_window()
450 PIPE_RESTORE(device, chan->lma_window, 0x6790); in nv17_gr_mthd_lma_window()
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/linux/drivers/video/fbdev/
H A Dgbefb.c4 * Copyright (C) 1999 Silicon Graphics, Inc. - Jeffrey Newquist
5 * Copyright (C) 2002 Vivien Chappelier <vivien.chappelier@linux-mips.org>
14 #include <linux/dma-mapping.h>
44 /* macro for fastest write-though access to the framebuffer */
63 #define TILE_MASK (TILE_SIZE - 1)
87 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
102 .height = -1,
103 .width = -1,
133 .height = -1,
134 .width = -1,
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/linux/drivers/gpu/drm/nouveau/include/nvkm/core/
H A Dengine.h1 /* SPDX-License-Identifier: MIT */
4 #define nvkm_engine(p) container_of((p), struct nvkm_engine, subdev) argument
27 void (*tile)(struct nvkm_engine *, int region, struct nvkm_fb_tile *); member
/linux/drivers/hwmon/
H A Dintel-m10-bmc-hwmon.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2020 Intel Corporation. All rights reserved.
10 #include <linux/mfd/intel-m10-bmc.h>
243 { 0x1a8, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-1 Temperature" },
244 { 0x1ac, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-2 Temperature" },
245 { 0x1b0, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-3 Temperature" },
246 { 0x1b4, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-4 Temperature" },
344 { 0x444, 0x448, 0x44c, 0x0, 0x0, 500, "FPGA E-TILE Temperature #1" },
345 { 0x450, 0x454, 0x458, 0x0, 0x0, 500, "FPGA E-TILE Temperature #2" },
346 { 0x45c, 0x460, 0x464, 0x0, 0x0, 500, "FPGA E-TILE Temperature #3" },
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/linux/arch/riscv/kernel/vdso/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0-only
2 # Copied from arch/tile/kernel/vdso/Makefile
7 vdso-syms = rt_sigreturn
9 vdso-syms += vgettimeofday
11 vdso-syms += getcpu
12 vdso-syms += flush_icache
13 vdso-syms += hwprobe
14 vdso-syms += sys_hwprobe
17 vdso-syms += getrandom
21 obj-vdso = $(patsubst %, %.o, $(vdso-syms)) note.o
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