On\-Chip (full) in projects: freebsd - OpenGrok search results

Project(s)

Full Search
Definition
Symbol
File Path
History
Type

Searched +full:on +full:- +full:chip (Results 1 – 25 of 1007) sorted by relevance

12 3 4 5 6 7 8 9 10 >>...41

/freebsd/lib/libpmc/pmu-events/arch/powerpc/power8/
H A D	other.json	11 …"BriefDescription": "Cycles in 2-lpar mode. Threads 0-3 belong to Lpar0 and threads 4-7 belong to … 17 …cles in 4 LPAR mode. Threads 0-1 belong to lpar0, threads 2-3 belong to lpar1, threads 4-5 belong … 23 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for all data … 24 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pum… 36 … got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump w… 41 …"BriefDescription": "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for a… 42 …urced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump w… 65 …ump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the origi… 66 …(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group… 71 …"BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group… [all …]
H A D	cache.json	5 …oaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), … 6 …oaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), … 11 …eloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), … 12 …eloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), … 17 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different… 18 …"PublicDescription": "The processor's data cache was reloaded from another chip's L4 on a differen… 29 "BriefDescription": "Demand LD - L2 Miss (not L2 hit)", 53 …ata cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to a … 54 …ata cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to ei… 71 "BriefDescription": "Demand LD - L3 Miss (not L2 hit and not L3 hit)", [all …]
H A D	frontend.json	47 "BriefDescription": "Number of I-ERAT reloads", 59 "BriefDescription": "IERAT Miss (Not implemented as DI on POWER6)", 71 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for an instru… 72 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pum… 89 …oaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), … 90 …oaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), … 95 …eloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), … 96 …eloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), … 101 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a di… 102 …"PublicDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a d… [all …]
/freebsd/lib/libpmc/pmu-events/arch/powerpc/power9/
H A D	translation.json	15 …data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a dema… 20 "BriefDescription": "Double-Precion or Quad-Precision instruction completed" 25 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the … 35 …o the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as… 60 …the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), … 75 …to the TLB either shared or modified data from another core's L2/L3 on the same chip due to a inst… 80 …tion cache was reloaded with Shared (S) data from another core's L2 on the same chip due to an ins… 95 …ta cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a dema… 100 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same… 130 "BriefDescription": "Demand LD - L2 Miss (not L2 hit)" [all …]
H A D	marked.json	20 …was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a data… 25 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam… 30 …"BriefDescription": "Completion stall by Dcache miss which resolved from remote chip (cache or mem… 60 …"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due… 70 …loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a mark… 95 …aded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a mark… 100 …loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a data… 120 …tion": "The processor's Instruction cache was reloaded from another chip's memory on the same Node… 130 …"BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to a… 145 …"BriefDescription": "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for a… [all …]
H A D	pipeline.json	10 "BriefDescription": "Number of I-ERAT reloads" 25 …"BriefDescription": "Finish stall because the NTF instruction was a multi-cycle instruction issued… 30 …s reloaded either shared or modified data from another core's L2/L3 on the same chip due to a mark… 35 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a differ… 80 …s loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a mark… 90 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different… 95 …s loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a data… 115 …as loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a… 135 …"BriefDescription": "Completion stall by Dcache miss which resolved on chip ( excluding local L2/L… 160 …o the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or … [all …]
H A D	cache.json	5 …ion": "PPC Instructions Finished by this thread when all threads in the core had the run-latch set" 25 …"BriefDescription": "Duration in cycles to reload from another chip's L4 on the same Node or Group… 40 …s reloaded either shared or modified data from another core's L2/L3 on the same chip due to an ins… 50 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on the … 55 … reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as… 70 …as loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a… 80 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the … 90 …"BriefDescription": "Finish stall because the NTF instruction was a load that hit on an older stor… 100 …eloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as…
/freebsd/share/man/man4/
H A D	ahc.4	22 .\" DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 .Bd -ragged -offset indent 48 .Bd -literal -offset indent 60 fast, ultra or ultra2 synchronous transfers depending on controller type, 64 .Tn SCSI-Select 72 For systems that store non-volatile settings in a system specific manner 78 many chip-down motherboard configurations. 86 by a particular chip, may be disabled in a particular motherboard or card 88 .Bd -ragged -offset indent 89 .Bl -column "aic7895CX" "MIPSX" "PCI/64X" "MaxSyncX" "MaxWidthX" "SCBsX" "2 3 4 5 6 7 8X" [all …]
H A D	acpi_hp.4	20 .\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 .Bd -ragged -offset indent 42 .Bd -literal -offset indent 48 driver provides support for ACPI-controlled features found on HP laptops 63 .Bl -tag -width "subsystem" -offset indent -compact 70 The value depends on the model. 77 .Bl -tag -width "0xc0" -offset indent -compact 79 WLAN on air status changed to 0 (not on air) 81 WLAN on air status changed to 1 (on air) 83 Bluetooth on air status changed to 0 (not on air) [all …]
/freebsd/lib/libpmc/pmu-events/arch/s390/cf_zec12/
H A D	extended.json	6 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB… 12 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle… 18 …on": "A directory write to the Level-1 Data cache directory where the returned cache line was sour… 24 … "A directory write to the Level-1 Instruction cache directory where the returned cache line was s… 30 …on": "A directory write to the Level-1 Data cache directory where the returned cache line was sour… 36 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi… 42 …"PublicDescription": "A directory write to the Level-1 Data cache where the installed cache line w… 48 …"PublicDescription": "A directory write to the Level-1 Instruction cache where the installed cache… 53 "BriefDescription": "L1D Read-only Exclusive Writes", 54 …PublicDescription": "A directory write to the Level-1 D-Cache where the line was originally in a R… [all …]
/freebsd/sys/contrib/device-tree/Bindings/net/nfc/
H A D	nfcmrvl.txt	4 - compatible: Should be: 5 - "marvell,nfc-uart" or "mrvl,nfc-uart" for UART devices 6 - "marvell,nfc-i2c" for I2C devices 7 - "marvell,nfc-spi" for SPI devices 10 - pinctrl-names: Contains only one value - "default". 11 - pintctrl-0: Specifies the pin control groups used for this controller. 12 - reset-n-io: Output GPIO pin used to reset the chip (active low). 13 - hci-muxed: Specifies that the chip is muxing NCI over HCI frames. 15 Optional UART-based chip specific properties: 16 - flow-control: Specifies that the chip is using RTS/CTS. [all …]
/freebsd/lib/libpmc/pmu-events/arch/s390/cf_z14/
H A D	extended.json	5 "BriefDescription": "L1D Read-only Exclusive Writes", 6 …blicDescription": "A directory write to the Level-1 Data cache where the line was originally in a … 18 …cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on this cycle" 23 "BriefDescription": "DTLB2 One-Megabyte Page Writes", 24 … into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page… 29 "BriefDescription": "DTLB2 Two-Gigabyte Page Writes", 30 …"PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB" 36 …on": "A directory write to the Level-1 Data cache directory where the returned cache line was sour… 48 …tion cache. Incremented by one for every TLB2 miss in progress for the Level-1 Instruction cache i… 54 … "A directory write to the Level-1 Instruction cache directory where the returned cache line was s… [all …]
/freebsd/sys/contrib/device-tree/Bindings/spi/
H A D	spi-sprd-adi.txt	3 ADI is the abbreviation of Anolog-Digital interface, which is used to access 4 analog chip (such as PMIC) from digital chip. ADI controller follows the SPI 9 48 hardware channels to access analog chip. For 2 software read/write channels, 10 users should set ADI registers to access analog chip. For hardware channels, 12 which means we can just link one analog chip address to one hardware channel, 13 then users can access the mapped analog chip address by this hardware channel 16 Thus we introduce one property named "sprd,hw-channels" to configure hardware 19 the analog chip address where user want to access by hardware components. 21 Since we have multi-subsystems will use unique ADI to access analog chip, when 34 - compatible: Should be "sprd,sc9860-adi". [all …]
/freebsd/sys/dev/ata/chipsets/
H A D	ata-acerlabs.c	`1 /- 2 SPDX-License-Identifier: BSD-2-Clause 4 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 48 #include <dev/ata/ata-all.h> 49 #include <dev/ata/ata-pci.h> 92 if (!(ctlr->chip = ata_match_chip(dev, ids))) in ata_ali_probe() 96 ctlr->chipinit = ata_ali_chipinit; in ata_ali_probe() 97 ctlr->chipdeinit = ata_ali_chipdeinit; in ata_ali_probe() 111 switch (ctlr->chip->cfg2) { in ata_ali_chipinit() [all …]`
/freebsd/lib/libpmc/pmu-events/arch/s390/cf_z13/
H A D	extended.json	5 "BriefDescription": "L1D Read-only Exclusive Writes", 6 …blicDescription": "A directory write to the Level-1 Data cache where the line was originally in a … 12 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi… 18 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB… 23 "BriefDescription": "DTLB1 One-Megabyte Page Writes", 24 …": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a on… 29 "BriefDescription": "DTLB1 Two-Gigabyte Page Writes", 30 …": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a tw… 36 …on": "A directory write to the Level-1 Data cache directory where the returned cache line was sour… 42 …"PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation … [all …]
/freebsd/lib/libpmc/pmu-events/arch/s390/cf_z196/
H A D	extended.json	6 …ion": "A directory write to the Level-1 D-Cache directory where the returned cache line was source… 12 …ion": "A directory write to the Level-1 I-Cache directory where the returned cache line was source… 18 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB… 24 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle… 30 "PublicDescription": "Incremented by one for every store sent to Level-2 cache" 35 "BriefDescription": "L1D Off-Book L3 Sourced Writes", 36 …: "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced fr… 41 "BriefDescription": "L1D On-Book L4 Sourced Writes", 42 …": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced f… 47 "BriefDescription": "L1I On-Book L4 Sourced Writes", [all …]
/freebsd/sys/dev/wbwd/
H A D	wbwd.c	`1 /- 2 SPDX-License-Identifier: BSD-2-Clause 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 88 #define WB_LDN8_CRF7_FORCE 0x20 /* 1: force timeout (self-clear) / 100 enum chips chip; member 109 re-load it periodically. 117 * register as these might be different by chip. 126 enum chips chip; member 131 .chip = w83627hf, 136 .chip = w83627s, [all …]`
/freebsd/sys/dev/bhnd/
H A D	bhnd_match.h	`1 /- 2 SPDX-License-Identifier: BSD-2-Clause 4 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org> 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 43 to match on any revision. / 45 to match on any revision. / 50 .m.match._name = (_src)->m.match._name, \ 51 ._name = (_src)->_name 62 ((_m)->start == BHND_HWREV_INVALID && (_m)->end == BHND_HWREV_INVALID) 69 * to match on any revision. [all …]`
/freebsd/sys/contrib/device-tree/Bindings/display/bridge/
H A D	adi,adv7511.txt	2 ------------------------------------------------ 11 - compatible: Should be one of: 18 - reg: I2C slave addresses 21 I2C address and acts as a standard slave device on the I2C bus. The main 28 arrangement of components on the data bus. The combination of the following 32 - adi,input-depth: Number of bits per color component at the input (8, 10 or 34 - adi,input-colorspace: The input color space, one of "rgb", "yuv422" or 36 - adi,input-clock: The input clock type, one of "1x" (one clock cycle per 38 data driven on both edges). 43 - adi,input-style: The input components arrangement variant (1, 2 or 3), as [all …]
/freebsd/share/man/man9/
H A D	bhnd.9	`1 .\" Copyright (c) 2015-2016 Landon Fuller <landonf@FreeBSD.org> 24 .\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 334 .Fa "const struct bhnd_chipid chip" "const struct bhnd_chip_match desc" 375 .Fa "chip" "hwrev" "flags" 390 .Fa "chip" "pkg" "flags" 392 .Bd -literal 398 .Bd -literal 406 .Bd -literal 414 .Bd -literal 417 .Bd -literal [all …]`
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A D	pinctrl-mcp23s08.txt	2 8-/16-bit I/O expander with serial interface (I2C/SPI) 5 - compatible : Should be 6 - "mcp,mcp23s08" (DEPRECATED) for 8 GPIO SPI version 7 - "mcp,mcp23s17" (DEPRECATED) for 16 GPIO SPI version 8 - "mcp,mcp23008" (DEPRECATED) for 8 GPIO I2C version or 9 - "mcp,mcp23017" (DEPRECATED) for 16 GPIO I2C version of the chip 11 - "microchip,mcp23s08" for 8 GPIO SPI version 12 - "microchip,mcp23s17" for 16 GPIO SPI version 13 - "microchip,mcp23s18" for 16 GPIO SPI version 14 - "microchip,mcp23008" for 8 GPIO I2C version or [all …]
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ddr/
H A D	jedec,lpddr-channel.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-channel.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: LPDDR channel with chip/rank topology description 13 amount of individual LPDDR chips and the ranks per chip. 16 - Julius Werner <jwerner@chromium.org> 21 - jedec,lpddr2-channel 22 - jedec,lpddr3-channel 23 - jedec,lpddr4-channel [all …]`
/freebsd/sys/contrib/device-tree/Bindings/net/
H A D	gpmc-eth.txt	1 Device tree bindings for Ethernet chip connected to TI GPMC 4 General-Purpose Memory Controller can be used to connect Pseudo-SRAM devices 12 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt 18 Child nodes need to specify the GPMC bus address width using the "bank-width" 20 specify the I/O registers address width. Even when the GPMC has a maximum 16-bit 21 address width, it supports devices with 32-bit word registers. 22 For example with an SMSC LAN911x/912x controller connected to the TI GPMC on an 23 OMAP2+ board, "bank-width = <2>;" and "reg-io-width = <4>;". 26 - bank-width: Address width of the device in bytes. GPMC supports 8-bit 27 and 16-bit devices and so must be either 1 or 2 bytes. [all …]
/freebsd/sys/contrib/device-tree/Bindings/mtd/
H A D	raw-nand-chip.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/mtd/raw-nand-chip.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Raw NAND Chip Common Properties 10 - Miquel Raynal <miquel.raynal@bootlin.com> 13 - $ref: nand-chip.yaml# 19 {size} bytes for a particular raw NAND chip. 21 The interpretation of these parameters is implementation-defined, so 28 pattern: "^nand@[a-f0-9]$" [all …]`
/freebsd/sys/contrib/device-tree/Bindings/bus/
H A D	qcom,ebi2.txt	4 external memory (such as NAND or other memory-mapped peripherals) whereas 9 data lines (16 bits), OE (output enable), ADV (address valid, used on some 10 NOR flash memories), WE (write enable). This on top of 6 different chip selects 13 Apparently this bus is clocked at 64MHz. It has dedicated pins on the package 14 and the bus can only come out on these pins, however if some of the pins are 18 Also CS1 and CS2 has -A and -B signals. Why they have that is unclear to me. 20 The chip selects have the following memory range assignments. This region of 21 memory is referred to as "Chip Peripheral SS FPB0" and is 168MB big. 23 Chip Select Physical address base 24 CS0 GPIO134 0x1a800000-0x1b000000 (8MB) [all …]

12 3 4 5 6 7 8 9 10 >>...41