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/linux/drivers/net/ethernet/mscc/
H A Docelot.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Microsemi Ocelot Switch driver
7 #include <linux/dsa/ocelot.h>
14 #include "ocelot.h"
30 /* Caller must hold &ocelot->mact_lock */
31 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot) in ocelot_mact_read_macaccess() argument
33 return ocelot_read(ocelot, ANA_TABLES_MACACCESS); in ocelot_mact_read_macaccess()
36 /* Caller must hold &ocelot->mact_lock */
37 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot) in ocelot_mact_wait_for_completion() argument
42 ocelot, val, in ocelot_mact_wait_for_completion()
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H A Docelot_vsc7514.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Microsemi Ocelot Switch driver
7 #include <linux/dsa/ocelot.h>
20 #include <soc/mscc/ocelot.h>
24 #include "ocelot.h"
29 static int ocelot_chip_init(struct ocelot *ocelot, const struct ocelot_ops *ops) in ocelot_chip_init() argument
33 ocelot->map = vsc7514_regmap; in ocelot_chip_init()
34 ocelot->num_mact_rows = 1024; in ocelot_chip_init()
35 ocelot->ops = ops; in ocelot_chip_init()
37 ret = ocelot_regfields_init(ocelot, vsc7514_regfields); in ocelot_chip_init()
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H A Docelot_fdma.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
13 #include <linux/dsa/ocelot.h>
22 static void ocelot_fdma_writel(struct ocelot *ocelot, u32 reg, u32 data) in ocelot_fdma_writel() argument
24 regmap_write(ocelot->targets[FDMA], reg, data); in ocelot_fdma_writel()
27 static u32 ocelot_fdma_readl(struct ocelot *ocelot, u32 reg) in ocelot_fdma_readl() argument
31 regmap_read(ocelot->targets[FDMA], reg, &retval); in ocelot_fdma_readl()
43 return (dma - base) / sizeof(struct ocelot_fdma_dcb); in ocelot_fdma_dma_idx()
48 return unlikely(idx == ring_sz - 1) ? 0 : idx + 1; in ocelot_fdma_idx_next()
53 return unlikely(idx == 0) ? ring_sz - 1 : idx - 1; in ocelot_fdma_idx_prev()
58 struct ocelot_fdma_rx_ring *rx_ring = &fdma->rx_ring; in ocelot_fdma_rx_ring_free()
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H A Docelot_devlink.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright 2020-2021 NXP
5 #include "ocelot.h"
9 * Resource 1: Frame references tracked per source port
17 #define REF_xxxx_I (1 * OCELOT_RESOURCE_SZ)
33 * ----------------------
128 * ------------------
153 (BUF_xxxx_E + xxx_COL_SHR_x + (1 - (dp)))
175 (BUF_xxxx_I + xxx_COL_SHR_x + (1 - (dp)))
197 (REF_xxxx_E + xxx_COL_SHR_x + (1 - (dp)))
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H A Docelot_mrp.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Microsemi Ocelot Switch driver
5 * Copyright 2020-2021 NXP
12 #include "ocelot.h"
18 static int ocelot_mrp_find_partner_port(struct ocelot *ocelot, in ocelot_mrp_find_partner_port() argument
23 for (i = 0; i < ocelot->num_phys_ports; ++i) { in ocelot_mrp_find_partner_port()
24 struct ocelot_port *ocelot_port = ocelot->ports[i]; in ocelot_mrp_find_partner_port()
29 if (ocelot_port->mrp_ring_id == p->mrp_ring_id) in ocelot_mrp_find_partner_port()
33 return -1; in ocelot_mrp_find_partner_port()
36 static int ocelot_mrp_del_vcap(struct ocelot *ocelot, int id) in ocelot_mrp_del_vcap() argument
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H A Docelot_ptp.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Microsemi Ocelot PTP clock driver
9 #include <linux/dsa/ocelot.h>
14 #include <soc/mscc/ocelot.h>
15 #include "ocelot.h"
21 struct ocelot *ocelot = container_of(ptp, struct ocelot, ptp_info); in ocelot_ptp_gettime64() local
27 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); in ocelot_ptp_gettime64()
29 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); in ocelot_ptp_gettime64()
32 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); in ocelot_ptp_gettime64()
34 s = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_MSB, TOD_ACC_PIN) & 0xffff; in ocelot_ptp_gettime64()
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H A Docelot_vcap.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Microsemi Ocelot Switch driver
24 VCAP_CMD_READ = 1, /* Copy from TCAM to Cache */
40 u32 tg_sw; /* Current type-group */
45 u32 tg_value; /* Current type-group value */
46 u32 tg_mask; /* Current type-group mask */
49 static u32 vcap_read_update_ctrl(struct ocelot *ocelot, in vcap_read_update_ctrl() argument
52 return ocelot_target_read(ocelot, vcap->target, VCAP_CORE_UPDATE_CTRL); in vcap_read_update_ctrl()
55 static void vcap_cmd(struct ocelot *ocelot, const struct vcap_props *vcap, in vcap_cmd() argument
62 if ((sel & VCAP_SEL_ENTRY) && ix >= vcap->entry_count) in vcap_cmd()
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H A Docelot_police.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Microsemi Ocelot Switch driver
7 #include <soc/mscc/ocelot.h>
10 /* Types for ANA:POL[0-192]:POL_MODE_CFG.FRM_MODE */
11 #define POL_MODE_LINERATE 0 /* Incl IPG. Unit: 33 1/3 kbps, 4096 bytes */
12 #define POL_MODE_DATARATE 1 /* Excl IPG. Unit: 33 1/3 kbps, 4096 bytes */
13 #define POL_MODE_FRMRATE_HI 2 /* Unit: 33 1/3 fps, 32.8 frames */
14 #define POL_MODE_FRMRATE_LO 3 /* Unit: 1/3 fps, 0.3 frames */
17 #define POL_IX_PORT 0 /* 0-11 : Port policers */
18 #define POL_IX_QUEUE 32 /* 32-127 : Queue policers */
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H A Docelot_mm.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Hardware library for MAC Merge Layer and Frame Preemption on TSN-capable
6 * Copyright 2022-2023 NXP
9 #include <soc/mscc/ocelot.h>
13 #include "ocelot.h"
39 case 1: in ocelot_mm_verify_status()
52 void ocelot_port_update_active_preemptible_tcs(struct ocelot *ocelot, int port) in ocelot_port_update_active_preemptible_tcs() argument
54 struct ocelot_port *ocelot_port = ocelot->ports[port]; in ocelot_port_update_active_preemptible_tcs()
55 struct ocelot_mm_state *mm = &ocelot->mm[port]; in ocelot_port_update_active_preemptible_tcs()
58 lockdep_assert_held(&ocelot->fwd_domain_lock); in ocelot_port_update_active_preemptible_tcs()
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H A Docelot_police.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2 /* Microsemi Ocelot Switch driver
10 #include "ocelot.h"
20 MSCC_QOS_RATE_MODE_MAX = __MSCC_QOS_RATE_MODE_END - 1,
34 int qos_policer_conf_set(struct ocelot *ocelot, u32 pol_ix,
/linux/include/soc/mscc/
H A Docelot.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
23 * - In one of PGID[0-63]: for the destination masks. There are 2 paths by
25 * - The {DMAC, VID} is present in the MAC table. In that case, the
28 * - The {DMAC, VID} is not present in the MAC table (it is unknown). The
34 * ocelot->num_phys_ports - 1, or a multicast set: the PGIDs from
35 * ocelot->num_phys_ports to 63. By convention, a unicast PGID corresponds to
40 * - In one of PGID[64-79]: for the aggregation mask. The switch classifier
41 * dissects each frame and generates a 4-bit Link Aggregation Code which is
48 * - In one of PGID[80-90]: for the source mask. The third time, the PGID table
60 * PGID_MC: the flooding destinations for non-IP multicast traffic.
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H A Docelot_vcap.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 * Microsemi Ocelot Switch driver
9 #include <soc/mscc/ocelot.h>
14 #define OCELOT_VCAP_ES0_TAG_8021Q_RXVLAN(ocelot, port, upstream) ((upstream) << 16 | (port)) argument
15 #define OCELOT_VCAP_IS1_TAG_8021Q_TXVLAN(ocelot, port) (port) argument
16 #define OCELOT_VCAP_IS1_VLAN_RECLASSIFY(ocelot, port) ((ocelot)->num_phys_ports + (port)) argument
17 #define OCELOT_VCAP_IS2_TAG_8021Q_TXVLAN(ocelot, port) (port) argument
18 #define OCELOT_VCAP_IS2_MRP_REDIRECT(ocelot, port) ((ocelot)->num_phys_ports + (port)) argument
19 #define OCELOT_VCAP_IS2_MRP_TRAP(ocelot) ((ocelot)->num_phys_ports * 2) argument
20 #define OCELOT_VCAP_IS2_L2_PTP_TRAP(ocelot) ((ocelot)->num_phys_ports * 2 + 1) argument
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H A Docelot_ptp.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
3 * Microsemi Ocelot Switch driver
14 #include <soc/mscc/ocelot.h>
44 #define PTP_CFG_CLK_ADJ_CFG_DIR BIT(1)
57 int ocelot_init_timestamp(struct ocelot *ocelot,
59 int ocelot_deinit_timestamp(struct ocelot *ocelot);
/linux/drivers/net/dsa/ocelot/
H A Dfelix_vsc9959.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright 2018-2019 NXP
13 #include <soc/mscc/ocelot.h>
14 #include <linux/dsa/ocelot.h>
15 #include <linux/pcs-lynx.h>
587 [ANA_ANEVENTS_SEQ_GEN_ERR_0] = REG_FIELD(ANA_ANEVENTS, 1, 1),
599 [QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 7, 4),
603 [SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 1, 2, 7, 4),
606 [SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 9, 7, 4),
607 [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 7, 4),
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H A Dfelix.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 #define ocelot_to_felix(o) container_of((o), struct felix, ocelot)
12 #define OCELOT_PORT_MODE_SGMII BIT(1)
20 /* Platform-specific information */
43 /* Some Ocelot switches are integrated into the SoC without the
55 int (*mdio_bus_alloc)(struct ocelot *ocelot);
56 void (*mdio_bus_free)(struct ocelot *ocelot);
59 void (*port_sched_speed_set)(struct ocelot *ocelot, int port,
61 void (*phylink_mac_config)(struct ocelot *ocelot, int port,
64 int (*configure_serdes)(struct ocelot *ocelot, int port,
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H A Docelot_ext.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright 2021-2022 Innovative Advantage Inc.
6 #include <linux/mfd/ocelot.h>
9 #include <soc/mscc/ocelot.h>
67 return felix_register_switch(&pdev->dev, 0, 1, false, false, in ocelot_ext_probe()
73 struct felix *felix = dev_get_drvdata(&pdev->dev); in ocelot_ext_remove()
78 dsa_unregister_switch(felix->ds); in ocelot_ext_remove()
83 struct felix *felix = dev_get_drvdata(&pdev->dev); in ocelot_ext_shutdown()
88 dsa_switch_shutdown(felix->ds); in ocelot_ext_shutdown()
90 dev_set_drvdata(&pdev->dev, NULL); in ocelot_ext_shutdown()
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/linux/Documentation/devicetree/bindings/mfd/
H A Dmscc,ocelot.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
3 ---
4 $id: http://devicetree.org/schemas/mfd/mscc,ocelot.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ocelot Externally-Controlled Ethernet Switch
10 - Colin Foster <colin.foster@in-advantage.com>
13 The Ocelot ethernet switch family contains chips that have an internal CPU
18 The switch family is a multi-port networking switch that supports many
25 - mscc,vsc7512
28 maxItems: 1
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/linux/arch/mips/boot/dts/mscc/
H A Docelot.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 #address-cells = <1>;
6 #size-cells = <1>;
7 compatible = "mscc,ocelot";
10 #address-cells = <1>;
11 #size-cells = <0>;
25 cpuintc: interrupt-controller {
26 #address-cells = <0>;
27 #interrupt-cells = <1>;
28 interrupt-controller;
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H A Docelot_pcb120.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/phy/phy-ocelot-serdes.h>
9 #include "ocelot.dtsi"
12 compatible = "mscc,ocelot-pcb120", "mscc,ocelot";
15 stdout-path = "serial0:115200n8";
25 phy_int_pins: phy-int-pins {
30 phy_load_save_pins: phy-load-save-pins {
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H A Djaguar2.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #address-cells = <1>;
8 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
29 cpuintc: interrupt-controller {
30 #address-cells = <0>;
31 #interrupt-cells = <1>;
32 interrupt-controller;
33 compatible = "mti,cpu-interrupt-controller";
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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dmscc,ocelot-icpu-intr.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/mscc,ocelot-icpu-intr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microsemi Ocelot SoC ICPU Interrupt Controller
10 - Alexandre Belloni <alexandre.belloni@bootlin.com>
13 - $ref: /schemas/interrupt-controller.yaml#
16 the Microsemi Ocelot interrupt controller that is part of the
23 - enum:
24 - mscc,jaguar2-icpu-intr
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/linux/Documentation/devicetree/bindings/i2c/
H A Dsnps,designware-i2c.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/i2c/snps,designware-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jarkko Nikula <jarkko.nikula@linux.intel.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
14 - if:
19 const: mscc,ocelot-i2c
23 maxItems: 1
28 - description: Generic Synopsys DesignWare I2C controller
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmscc,ocelot-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mscc,ocelot-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microsemi Ocelot pin controller
10 - Alexandre Belloni <alexandre.belloni@bootlin.com>
11 - Lars Povlsen <lars.povlsen@microchip.com>
16 - enum:
17 - microchip,lan966x-pinctrl
18 - microchip,lan9691-pinctrl
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/linux/drivers/power/reset/
H A Docelot-reset.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
37 #define IF_SI_OWNER_MASK GENMASK(1, 0)
39 #define IF_SI_OWNER_SIBM 1
48 u32 if_si_owner_bit = ctx->props->if_si_owner_bit; in ocelot_restart_handle()
51 regmap_update_bits(ctx->cpu_ctrl, ctx->props->protect_reg, in ocelot_restart_handle()
52 ctx->props->vcore_protect, 0); in ocelot_restart_handle()
56 regmap_update_bits(ctx->cpu_ctrl, in ocelot_restart_handle()
63 writel(SOFT_CHIP_RST, ctx->base); in ocelot_restart_handle()
72 struct device *dev = &pdev->dev; in ocelot_reset_probe()
75 ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL); in ocelot_reset_probe()
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/linux/drivers/mfd/
H A Docelot-spi.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * SPI core driver for the Ocelot chip family.
11 * Copyright 2021-2022 Innovative Advantage Inc.
13 * Author: Colin Foster <colin.foster@in-advantage.com>
28 #include "ocelot.h"
34 #define CFGSTAT_IF_NUM_VRAP (1 << 24)
63 * The SPI address must be big-endian, but we want the payload to match in ocelot_spi_initialize()
64 * our CPU. These are two bits (0 and 1) but they're repeated such that in ocelot_spi_initialize()
68 * 0b00: little-endian, MSB first in ocelot_spi_initialize()
72 * 0b01: big-endian, MSB first in ocelot_spi_initialize()
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