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/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dmscc,ocelot.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
3 ---
4 $id: http://devicetree.org/schemas/mfd/mscc,ocelot.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ocelot Externally-Controlled Ethernet Switch
10 - Colin Foster <colin.foster@in-advantage.com>
13 The Ocelot ethernet switch family contains chips that have an internal CPU
18 The switch family is a multi-port networking switch that supports many
25 - mscc,vsc7512
28 maxItems: 1
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H A Dsyscon.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 represent as any specific type of device. The typical use-case is
13 for some other node's driver, or platform-specific code, to acquire
20 - Lee Jones <lee@kernel.org>
30 - al,alpine-sysfabric-servic
31 - allwinner,sun8i-a83t-system-controller
32 - allwinner,sun8i-h3-system-controller
33 - allwinner,sun8i-v3s-system-controller
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/freebsd/sys/contrib/device-tree/src/mips/mscc/
H A Docelot.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 #address-cells = <1>;
6 #size-cells = <1>;
7 compatible = "mscc,ocelot";
10 #address-cells = <1>;
11 #size-cells = <0>;
25 cpuintc: interrupt-controller {
26 #address-cells = <0>;
27 #interrupt-cells = <1>;
28 interrupt-controller;
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H A Docelot_pcb120.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/phy/phy-ocelot-serdes.h>
9 #include "ocelot.dtsi"
12 compatible = "mscc,ocelot-pcb120", "mscc,ocelot";
15 stdout-path = "serial0:115200n8";
25 phy_int_pins: phy-int-pins {
30 phy_load_save_pins: phy-load-save-pins {
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H A Djaguar2.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #address-cells = <1>;
8 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
29 cpuintc: interrupt-controller {
30 #address-cells = <0>;
31 #interrupt-cells = <1>;
32 interrupt-controller;
33 compatible = "mti,cpu-interrupt-controller";
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H A Dluton.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 #address-cells = <1>;
6 #size-cells = <1>;
10 #address-cells = <1>;
11 #size-cells = <0>;
25 cpuintc: interrupt-controller {
26 #address-cells = <0>;
27 #interrupt-cells = <1>;
28 interrupt-controller;
29 compatible = "mti,cpu-interrupt-controller";
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H A Dserval.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
28 cpuintc: interrupt-controller {
29 #address-cells = <0>;
30 #interrupt-cells = <1>;
31 interrupt-controller;
32 compatible = "mti,cpu-interrupt-controller";
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/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dmscc,ocelot-icpu-intr.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/mscc,ocelot-icpu-intr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microsemi Ocelot SoC ICPU Interrupt Controller
10 - Alexandre Belloni <alexandre.belloni@bootlin.com>
13 - $ref: /schemas/interrupt-controller.yaml#
16 the Microsemi Ocelot interrupt controller that is part of the
23 - enum:
24 - mscc,jaguar2-icpu-intr
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H A Dmscc,ocelot-icpu-intr.txt1 Microsemi Ocelot SoC ICPU Interrupt Controller
5 - compatible : should be "mscc,ocelot-icpu-intr"
6 - reg : Specifies base physical address and size of the registers.
7 - interrupt-controller : Identifies the node as an interrupt controller
8 - #interrupt-cells : Specifies the number of cells needed to encode an
9 interrupt source. The value shall be 1.
10 - interrupts : Specifies the CPU interrupt the controller is connected to.
14 intc: interrupt-controller@70000070 {
15 compatible = "mscc,ocelot-icpu-intr";
17 #interrupt-cells = <1>;
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/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dphy-ocelot-serdes.txt1 Microsemi Ocelot SerDes muxing driver
2 -------------------------------------
4 On Microsemi Ocelot, there is a handful of registers in HSIO address
13 half/full-duplex and 1000Mbps in full-duplex mode while SERDES6G supports
14 10/100Mbps in half/full-duplex and 1000/2500Mbps in full-duplex mode.
19 This is a child of the HSIO syscon ("mscc,ocelot-hsio", see
20 Documentation/devicetree/bindings/mips/mscc.txt) on the Microsemi Ocelot.
24 - compatible: should be "mscc,vsc7514-serdes"
25 - #phy-cells : from the generic phy bindings, must be 2.
28 defined in dt-bindings/phy/phy-ocelot-serdes.h
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/freebsd/sys/contrib/device-tree/Bindings/i2c/
H A Dsnps,designware-i2c.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/i2c/snps,designware-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jarkko Nikula <jarkko.nikula@linux.intel.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
14 - if:
19 const: mscc,ocelot-i2c
23 maxItems: 1
28 - description: Generic Synopsys DesignWare I2C controller
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/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dmscc,ocelot-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mscc,ocelot-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microsemi Ocelot pin controller
10 - Alexandre Belloni <alexandre.belloni@bootlin.com>
11 - Lars Povlsen <lars.povlsen@microchip.com>
16 - microchip,lan966x-pinctrl
17 - microchip,sparx5-pinctrl
18 - mscc,jaguar2-pinctrl
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H A Dmicrochip,sparx5-sgpio.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/microchip,sparx5-sgpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lars Povlsen <lars.povlsen@microchip.com>
21 pattern: "^gpio@[0-9a-f]+$"
25 - microchip,sparx5-sgpio
26 - mscc,ocelot-sgpio
27 - mscc,luton-sgpio
29 "#address-cells":
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/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dmscc-miim.txt5 - compatible: must be "mscc,ocelot-miim" or "microchip,lan966x-miim"
6 - reg: The base address of the MDIO bus controller register bank. Optionally, a
9 - #address-cells: Must be <1>.
10 - #size-cells: Must be <0>. MDIO addresses have no size component.
11 - interrupts: interrupt specifier (refer to the interrupt binding)
17 #address-cells = <1>;
18 #size-cells = <0>;
19 compatible = "mscc,ocelot-miim";
23 phy0: ethernet-phy@0 {
H A Dmscc,miim.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Belloni <alexandre.belloni@bootlin.com>
13 - $ref: mdio.yaml#
18 - mscc,ocelot-miim
19 - microchip,lan966x-miim
21 "#address-cells":
22 const: 1
24 "#size-cells":
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H A Dmscc-ocelot.txt1 Microsemi Ocelot network Switch
4 The Microsemi Ocelot network switch can be found on Microsemi SoCs (VSC7513,
8 - compatible: Should be "mscc,vsc7514-switch"
9 - reg: Must contain an (offset, length) pair of the register set for each
10 entry in reg-names.
11 - reg-names: Must include the following entries:
12 - "sys"
13 - "rew"
14 - "qs"
15 - "ptp" (optional due to backward compatibility)
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/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dsnps,dw-apb-ssi.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Brown <broonie@kernel.org>
13 - $ref: spi-controller.yaml#
14 - if:
19 - mscc,ocelot-spi
20 - mscc,jaguar2-spi
25 - if:
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/freebsd/sys/contrib/device-tree/Bindings/net/dsa/
H A Docelot.txt1 Microchip Ocelot switch driver family
5 -----
9 - VSC9959 (Felix)
10 - VSC9953 (Seville)
13 larger ENETC root complex. As a result, the ethernet-switch node is a sub-node
25 For the external switch ports, depending on board configuration, "phy-mode" and
26 "phy-handle" are populated by board specific device tree instances. Ports 4 and
30 the Ocelot hardware core. The CPU port in Ocelot is a set of queues, which are
32 By default, in fsl-ls1028a.dtsi, the NPI port is assigned to the internal
33 2.5Gbps port@4, but can be moved to the 1Gbps port@5, depending on the specific
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H A Ddsa-port.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/dsa/dsa-port.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Vladimir Oltean <olteanv@gmail.com>
17 DSA-specific functionality.
19 $ref: /schemas/net/ethernet-switch-port.yaml#
24 - description: Port number
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H A Dmscc,ocelot.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/net/dsa/mscc,ocelot.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip Ocelot Switch Family
10 - Vladimir Oltean <vladimir.oltean@nxp.com>
11 - Claudiu Manoil <claudiu.manoil@nxp.com>
12 - Alexandre Belloni <alexandre.belloni@bootlin.com>
13 - UNGLinuxDriver@microchip.com
16 There are multiple switches which are either part of the Ocelot-1 family, or
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/freebsd/share/man/man4/man4.aarch64/
H A Dfelix.41 .\" -
2 .\" SPDX-License-Identifier: BSD-2-Clause
10 .\" 1. Redistributions of source code must retain the above copyright
33 .Nd "driver for Microchip Ocelot Felix switch"
48 driver provides a management interface to Microchip Ocelot Felix switch (VSC9959)
67 .Dl # etherswitchcfg port5 -addtag
/freebsd/sys/contrib/device-tree/src/arm64/microchip/
H A Dsparx5.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/microchip,sparx5.h>
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <1>;
23 stdout-path = "serial0:115200n8";
27 #address-cells = <1>;
28 #size-cells = <0>;
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/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dfsl-ls1028a-kontron-sl28.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Device Tree file for the Kontron SMARC-sAL28 board.
9 /dts-v1/;
10 #include "fsl-ls1028a.dtsi"
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-binding
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