Home
last modified time | relevance | path

Searched +full:mali +full:- +full:dp500 (Results 1 – 8 of 8) sorted by relevance

/linux/Documentation/devicetree/bindings/display/
H A Darm,malidp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Arm Mali Display Processor (Mali-DP)
10 - Liviu Dudau <Liviu.Dudau@arm.com>
11 - Andre Przywara <andre.przywara@arm.com>
15 licensable IP by ARM Ltd. The bindings describe the Mali DP500, DP550 and
22 - arm,mali-dp500
23 - arm,mali-dp550
24 - arm,mali-dp650
[all …]
/linux/drivers/gpu/drm/arm/
H A Dmalidp_drv.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * ARM Mali DP500/DP550/DP650 KMS/DRM driver
56 hwdev->hw->map.coeffs_base + MALIDP_COEF_TABLE_ADDR); in malidp_write_gamma_table()
59 hwdev->hw->map.coeffs_base + in malidp_write_gamma_table()
67 struct malidp_hw_device *hwdev = malidp->dev; in malidp_atomic_commit_update_gamma()
69 if (!crtc->state->color_mgmt_changed) in malidp_atomic_commit_update_gamma()
72 if (!crtc->state->gamma_lut) { in malidp_atomic_commit_update_gamma()
78 to_malidp_crtc_state(crtc->state); in malidp_atomic_commit_update_gamma()
80 if (!old_state->gamma_lut || (crtc->state->gamma_lut->base.id != in malidp_atomic_commit_update_gamma()
81 old_state->gamma_lut->base.id)) in malidp_atomic_commit_update_gamma()
[all …]
H A Dmalidp_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * ARM Mali DP500/DP550/DP650 registers definition.
14 * - DC - display core (general settings)
15 * - DE - display engine
16 * - SE - scaling engine
170 /* register offsets and bits specific to DP500 */
190 * The YUV2RGB coefficients on the DP500 are not in the video layer's register
194 #define MALIDP500_LV_YUV2RGB ((s16)(-0xB8))
214 * The quality of service (QoS) register on the DP500. RQOS register values
218 * - RED_ARQOS @ A 4-bit signal value for close to underflow conditions
[all …]
H A Dmalidp_hw.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * (C) COPYRIGHT 2013-2016 ARM Limited. All rights reserved.
6 * ARM Mali DP hardware manipulation routines.
18 /* Mali DP IP blocks */
25 /* Mali DP layer IDs */
29 DE_GRAPHICS2 = BIT(2), /* used only in DP500 */
66 s16 yuv2rgb_offset; /* offset to the YUV->RGB matrix entries */
132 /* Unlike DP550/650, DP500 has 3 stride registers in its video layer. */
195 * @param hwdev - malidp_hw_device structure containing the HW description
196 * @param addrs - array of addresses for each plane
[all …]
H A Dmalidp_drv.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * ARM Mali DP500/DP550/DP650 KMS/DRM driver structures
H A Dmalidp_hw.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * ARM Mali DP500/DP550/DP650 hardware manipulation routines. This is where
29 MW_ONESHOT, /* SE in one-shot mode for writeback */
196 [MALIDP_UPSCALING_COEFFS - 1] = {
210 [MALIDP_DOWNSCALING_1_5_COEFFS - 1] = {
224 [MALIDP_DOWNSCALING_2_COEFFS - 1] = {
238 [MALIDP_DOWNSCALING_2_75_COEFFS - 1] = {
252 [MALIDP_DOWNSCALING_4_COEFFS - 1] = {
276 hwdev->min_line_size = 2; in malidp500_query_hw()
277 hwdev->max_line_size = SZ_2K * ln_size_mult; in malidp500_query_hw()
[all …]
H A Dmalidp_crtc.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * ARM Mali DP500/DP550/DP650 driver (crtc operations)
29 struct malidp_hw_device *hwdev = malidp->dev; in malidp_crtc_mode_valid()
35 long rate, req_rate = mode->crtc_clock * 1000; in malidp_crtc_mode_valid()
38 rate = clk_round_rate(hwdev->pxlclk, req_rate); in malidp_crtc_mode_valid()
53 struct malidp_hw_device *hwdev = malidp->dev; in malidp_crtc_atomic_enable()
55 int err = pm_runtime_get_sync(crtc->dev->dev); in malidp_crtc_atomic_enable()
62 drm_display_mode_to_videomode(&crtc->state->adjusted_mode, &vm); in malidp_crtc_atomic_enable()
63 clk_prepare_enable(hwdev->pxlclk); in malidp_crtc_atomic_enable()
66 clk_set_rate(hwdev->pxlclk, crtc->state->adjusted_mode.crtc_clock * 1000); in malidp_crtc_atomic_enable()
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1028a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1028A family SoC.
5 * Copyright 2018-2020 NXP
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <1>;
[all …]