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/freebsd/sys/contrib/device-tree/Bindings/display/bridge/
H A Dfsl,imx8qxp-ldb.yaml7 title: Freescale i.MX8qm/qxp LVDS Display Bridge
13 The Freescale i.MX8qm/qxp LVDS Display Bridge(LDB) has two channels.
15 The i.MX8qm/qxp LDB is controlled by Control and Status Registers(CSR) module.
27 For i.MX8qm LDB, each channel additionally supports up to 30bpp parallel
33 A side note is that i.MX8qm/qxp LDB is officially called pixel mapper in
H A Dfsl,imx8qxp-pixel-link.yaml7 title: Freescale i.MX8qm/qxp Display Pixel Link
13 The Freescale i.MX8qm/qxp Display Pixel Link(DPL) forms a standard
21 The i.MX8qm/qxp Display Pixel Link is accessed via System Controller Unit(SCU)
H A Dfsl,imx8qxp-pixel-combiner.yaml7 title: Freescale i.MX8qm/qxp Pixel Combiner
13 The Freescale i.MX8qm/qxp Pixel Combiner takes two output streams from a
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dfsl,imx8qm-lvds-phy.yaml7 title: Mixel LVDS PHY for Freescale i.MX8qm SoC
13 The Mixel LVDS PHY IP block is found on Freescale i.MX8qm SoC.
23 The Mixel LVDS PHY found on Freescale i.MX8qm SoC is controlled
H A Dfsl,imx8qm-hsio.yaml7 title: Freescale i.MX8QM SoC series High Speed IO(HSIO) SERDES PHY
50 Regarding the design of i.MX8QM HSIO subsystem, HSIO module can be
53 | | i.MX8QM |
/freebsd/sys/contrib/device-tree/Bindings/ata/
H A Dimx-sata.yaml67 Since "REXT" pin is only present for first lane of i.MX8QM PHY, it's
71 - description: phandle to the first lane PHY of i.MX8QM.
72 - description: phandle to the second lane PHY of i.MX8QM.
/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dfsl,imx8qxp-csr.yaml7 title: Freescale i.MX8qm/qxp Control and Status Registers Module
13 As a system controller, the Freescale i.MX8qm/qxp Control and Status
/freebsd/sys/contrib/device-tree/Bindings/media/
H A Damphion,vpu.yaml53 separately. NXP i.MX8QM SoC has one decoder and two encoder, i.MX8QXP SoC
110 # Device node example for i.MX8QM platform:
/freebsd/sys/contrib/device-tree/Bindings/bus/
H A Dfsl,imx8qxp-pixel-link-msi-bus.yaml24 Peripherals in i.MX8qm/qxp imaging, LVDS, MIPI DSI and HDMI TX subsystems,
28 The i.MX System Controller Firmware (SCFW) owns and uses the i.MX8qm/qxp
/freebsd/sys/contrib/device-tree/Bindings/i2c/
H A Di2c-imx-lpi2c.txt7 - "fsl,imx8qm-lpi2c" for LPI2C compatible with the one integrated on i.MX8QM soc
/freebsd/sys/contrib/device-tree/Bindings/serial/
H A Dfsl-lpuart.txt16 on i.MX8QM SoC with 32-bit little-endian register organization
/freebsd/sys/contrib/device-tree/Bindings/pwm/
H A Dpwm-fsl-ftm.txt22 - "fsl,imx8qm-ftm-pwm" for PWM compatible with the one integrated on i.MX8QM
/freebsd/sys/contrib/device-tree/Bindings/firmware/
H A Dfsl,scu.yaml15 resource management. It exists on some i.MX8 processors. e.g. i.MX8QM
/freebsd/sys/contrib/device-tree/Bindings/arm/freescale/
H A Dfsl,scu.txt6 resource management. It exists on some i.MX8 processors. e.g. i.MX8QM
/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dfsl.yaml1222 - description: i.MX8QM based Boards
1225 - fsl,imx8qm-mek # i.MX8QM MEK Board
1230 - description: i.MX8QM Boards with Toradex Apalis iMX8 Modules
1239 - description: i.MX8QM Boards with Toradex Apalis iMX8 V1.1 Modules
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8qm-mek.dts13 model = "Freescale i.MX8QM MEK";