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Searched full:mstp (Results 1 – 25 of 25) sorted by relevance

/linux/arch/sh/kernel/cpu/sh4a/
H A Dclock-sh7343.c125 #define MSTP(_parent, _reg, _bit, _flags) \ macro
139 [MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
140 [MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
141 [MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
142 [MSTP028] = MSTP(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
143 [MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
144 [MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
145 [MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
146 [MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
147 [MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
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H A Dclock-sh7366.c128 #define MSTP(_parent, _reg, _bit, _flags) \ macro
142 [MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
143 [MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
144 [MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
145 [MSTP028] = MSTP(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
146 [MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
147 [MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
148 [MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
149 [MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
150 [MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
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H A Dubc.c104 * The UBC MSTP bit is optional, as not all platforms will have in sh4a_ubc_init()
H A Dclock-sh7722.c190 /* MSTP clocks */
H A Dclock-sh7723.c215 /* MSTP clocks */
H A Dclock-sh7724.c281 /* MSTP clocks */
/linux/Documentation/devicetree/bindings/clock/
H A Drenesas,cpg-mstp-clocks.yaml4 $id: http://devicetree.org/schemas/clock/renesas,cpg-mstp-clocks.yaml#
7 title: Renesas Clock Pulse Generator (CPG) Module Stop (MSTP) Clocks
17 Clocks are referenced by user nodes by the Module Stop (MSTP) node phandle
24 - renesas,r7s72100-mstp-clocks # RZ/A1
25 - renesas,r8a73a4-mstp-clocks # R-Mobile APE6
26 - renesas,r8a7740-mstp-clocks # R-Mobile A1
27 - renesas,r8a7778-mstp-clocks # R-Car M1
28 - renesas,r8a7779-mstp-clocks # R-Car H1
29 - renesas,sh73a0-mstp-clocks # SH-Mobile AG5
30 - const: renesas,cpg-mstp-clocks
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H A Drenesas,cpg-clocks.yaml17 the CPG Module Stop (MSTP) Clocks.
/linux/drivers/clk/renesas/
H A Dclk-mstp.c3 * R-Car MSTP clocks
25 * MSTP clocks. We can't use standard gate clocks as we need to poll on the
32 * struct mstp_clock_group - MSTP gating clocks group
51 * struct mstp_clock - MSTP gating clock
54 * @group: MSTP clocks group
162 pr_debug("MSTP %s setting CLK_IS_CRITICAL\n", name); in cpg_mstp_clock_register()
204 if (of_device_is_compatible(np, "renesas,r7s72100-mstp-clocks")) in cpg_mstp_clocks_init()
250 CLK_OF_DECLARE(cpg_mstp_clks, "renesas,cpg-mstp-clocks", cpg_mstp_clocks_init);
263 "renesas,cpg-mstp-clocks")) in cpg_mstp_attach_dev()
266 /* BSC on r8a73a4/sh73a0 uses zb_clk instead of an mstp clock */ in cpg_mstp_attach_dev()
H A Drenesas-cpg-mssr.c7 * Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c
181 * struct mstp_clock - MSTP gating clock
183 * @index: MSTP clock number
206 dev_dbg(dev, "MSTP %u%02u/%pC %s\n", reg, bit, hw->clk, in cpg_mstp_clock_endisable()
454 dev_dbg(dev, "MSTP %s setting CLK_IS_CRITICAL\n", in cpg_mssr_register_mod_clk()
H A DMakefile54 obj-$(CONFIG_CLK_RENESAS_CPG_MSTP) += clk-mstp.o
H A DKconfig251 bool "MSTP clock support" if COMPILE_TEST
H A Drzg2l-cpg.c1178 * struct mstp_clock - MSTP gating clock
1184 * @priv: CPG/MSTP private data
/linux/include/dt-bindings/clock/
H A Dr8a7779-clock.h21 /* MSTP 0 */
40 /* MSTP 1 */
52 /* MSTP 3 */
/linux/arch/arm/boot/dts/renesas/
H A Dr8a7740.dtsi642 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
653 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
671 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
699 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
721 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
/linux/arch/sh/include/asm/
H A Dhw_breakpoint.h40 struct clk *clk; /* optional interface clock / MSTP bit */
/linux/arch/sh/kernel/cpu/sh2a/
H A Dclock-sh7264.c114 /* MSTP clocks */
H A Dclock-sh7269.c149 /* MSTP clocks */
/linux/include/linux/
H A Dsh_clk.h141 * MSTP registration never really cared about access size, despite the
/linux/drivers/pmdomain/renesas/
H A Drcar-sysc.c369 "renesas,cpg-mstp-clocks"); in rcar_sysc_pd_init()
/linux/Documentation/networking/
H A Dbridge.rst61 `Multiple Spanning Tree Protocol (MSTP)
/linux/arch/sh/drivers/pci/
H A Dpcie-sh7786.c572 * of touching the existing MSTP bits or CPG clocks. in sh7786_pcie_init()
/linux/drivers/net/dsa/microchip/
H A Dksz_common.h331 u8 mstp:3; member
H A Dksz9477.c662 alu->mstp = alu_table[0] & ALU_V_MSTP_M; in ksz9477_convert_alu()
/linux/drivers/net/dsa/realtek/
H A Drtl8365mb.c287 /* MSTP port state registers - indexed by tree instance */