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Searched full:msir (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/irqchip/
H A Dirq-ls-scfg-msi.c33 u32 msir_irqs; /* The irq number per MSIR */
34 u32 msir_base; /* The base address of MSIR */
55 struct ls_scfg_msir *msir; member
121 if (msi_data->msir[cpu].gic_irq <= 0) { in ls_scfg_msi_set_affinity()
196 struct ls_scfg_msir *msir = irq_desc_get_handler_data(desc); in ls_scfg_msi_irq_handler() local
197 struct ls_scfg_msi *msi_data = msir->msi_data; in ls_scfg_msi_irq_handler()
203 val = ioread32be(msir->reg); in ls_scfg_msi_irq_handler()
205 pos = msir->bit_start; in ls_scfg_msi_irq_handler()
206 size = msir->bit_end + 1; in ls_scfg_msi_irq_handler()
209 hwirq = ((msir->bit_end - pos) << msi_data->cfg->ibs_shift) | in ls_scfg_msi_irq_handler()
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/linux/drivers/pci/controller/
H A Dpci-xgene-msi.c133 u32 frame, msir; in xgene_compose_msi_msg() local
137 msir = FIELD_GET(MSInRx_HWIRQ_MASK, data->hwirq); in xgene_compose_msi_msg()
142 FIELD_PREP(MSI_INTR_MASK, msir)); in xgene_compose_msi_msg()
261 unsigned long msir; in xgene_msi_isr() local
264 msir = xgene_msi_ir_read(xgene_msi, msi_grp, msir_idx); in xgene_msi_isr()
266 for_each_set_bit(intr_idx, &msir, IRQS_PER_IDX) { in xgene_msi_isr()
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dfsl,mpic-msi.yaml37 primary window used for memory, but mapped to the MSIR block (where MSIIR
100 has created an alternate mapping for the MSIR block. See the top-level
/linux/arch/powerpc/kvm/
H A Dmpic.c232 uint32_t msir; /* Shared Message Signaled Interrupt Register */ member
955 opp->msi[srs].msir |= 1 << ibs; in openpic_msi_write()
987 r = opp->msi[srs].msir; in openpic_msi_read()
989 opp->msi[srs].msir = 0; in openpic_msi_read()
994 r |= (opp->msi[i].msir ? 1 : 0) << i; in openpic_msi_read()
/linux/arch/powerpc/sysdev/
H A Dfsl_msi.c47 u32 msiir_offset; /* Offset of MSIIR, relative to start of MSIR bank */
62 * We do not need this actually. The MSIR register has been read once
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192se/
H A Dreg.h191 #define MSIR 0x0224 macro