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/freebsd/sys/x86/x86/
H A Dmsi.c34 * Support for PCI Message Signalled Interrupts (MSI). MSI interrupts on
63 /* Fields in address for Intel MSI messages. */
72 /* Fields in data for Intel MSI messages. */
89 * Build Intel MSI message and data values from a source. AMD64 systems
92 #define INTEL_ADDR(msi) \ argument
93 (MSI_INTEL_ADDR_BASE | (msi)->msi_cpu << 12 | \
95 #define INTEL_DATA(msi) \ argument
96 (MSI_INTEL_DATA_TRGREDG | MSI_INTEL_DATA_DELFIXED | (msi)->msi_vector)
98 static MALLOC_DEFINE(M_MSI, "msi", "PCI MSI");
101 * MSI sources are bunched into groups. This is because MSI forces
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/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dpci-msi.txt2 relationship between PCI devices and MSI controllers.
18 Requester ID. A mechanism is required to associate a device with both the MSI
22 For generic MSI bindings, see
23 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
32 - msi-map: Maps a Requester ID to an MSI controller and associated
33 msi-specifier data. The property is an arbitrary number of tuples of
34 (rid-base,msi-controller,msi-base,length), where:
38 * msi-controller is a single phandle to an MSI controller
40 * msi-base is an msi-specifier describing the msi-specifier produced for the
47 the listed msi-controller, with the msi-specifier (r - rid-base + msi-base).
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H A Dbrcm,iproc-pcie.txt44 MSI support (optional):
46 For older platforms without MSI integrated in the GIC, iProc PCIe core provides
47 an event queue based MSI support. The iProc MSI uses host memories to store
48 MSI posted writes in the event queues
50 On newer iProc platforms, gicv2m or gicv3-its based MSI support should be used
52 - msi-map: Maps a Requester ID to an MSI controller and associated MSI
55 - msi-parent: Link to the device node of the MSI controller, used when no MSI
56 sideband data is passed between the iProc PCIe controller and the MSI
60 the use of 'msi-map' and 'msi-parent':
61 Documentation/devicetree/bindings/pci/pci-msi.txt
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H A Dxgene-pci-msi.txt1 * AppliedMicro X-Gene v1 PCIe MSI controller
5 - compatible: should be "apm,xgene1-msi" to identify
6 X-Gene v1 PCIe MSI controller block.
7 - msi-controller: indicates that this is an X-Gene v1 PCIe MSI controller node
9 registers. These registers include the MSI termination address and data
10 registers as well as the MSI interrupt status registers.
16 Each PCIe node needs to have property msi-parent that points to an MSI
23 + MSI node:
24 msi@79000000 {
25 compatible = "apm,xgene1-msi";
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H A Dpci-ep.yaml24 - description: Device ID (see msi-map) base
56 msi-map:
58 Maps a Device ID to an MSI and associated MSI specifier data.
60 A PCI Endpoint (EP) can use MSI as a doorbell function. This is achieved by
61 mapping the MSI controller's address into PCI BAR<n>. The PCI Root Complex
82 (device-id-base, msi, msi-base,length).
85 associated with the listed MSI, with the MSI specifier
86 (id - id-base + msi-base).
92 - description: phandle to msi-controller node
93 - description: (optional) The msi-specifier produced for the first
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H A Dbrcm,iproc-pcie.yaml63 msi:
65 $ref: /schemas/interrupt-controller/msi-controller.yaml#
71 - const: brcm,iproc-msi
76 brcm,pcie-msi-inten:
80 interrupt enable registers to be set explicitly to enable MSI
82 msi-parent: true
86 brcm,pcie-msi-inten: [msi-controller]
139 msi-parent = <&msi0>;
141 /* iProc event queue based MSI */
142 msi0: msi {
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H A Daltr,msi-controller.yaml5 $id: http://devicetree.org/schemas/altr,msi-controller.yaml#
8 title: Altera PCIe MSI controller
16 - altr,msi-1.0
31 msi-controller: true
44 - msi-controller
48 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
56 msi@ff200000 {
57 compatible = "altr,msi-1.0";
63 msi-controller;
/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dmsi.txt1 This document describes the generic device tree binding for MSI controllers and
9 those busses to the MSI controllers which they are capable of using,
17 they can address. An MSI controller may feature a number of doorbells.
22 MSI controllers may have restrictions on permitted payloads.
28 MSI controller and device rather than a property of either in isolation).
31 MSI controllers:
34 An MSI controller signals interrupts to a CPU when a write is made to an MMIO
35 address by some master. An MSI controller may feature a number of doorbells.
40 - msi-controller: Identifies the node as an MSI controller.
45 - #msi-cells: The number of cells in an msi-specifier, required if not zero.
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H A Dfsl,mpic-msi.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,mpic-msi.yaml#
7 title: Freescale MSI interrupt controller
10 The Freescale hypervisor and msi-address-64
14 Freescale MSI driver calculates the address of MSIIR (in the MSI register
15 block) and sets that address as the MSI message address.
39 this. The address specified in the msi-address-64 property is the PCI
50 - fsl,mpic-msi
51 - fsl,mpic-msi-v4.3
52 - fsl,ipic-msi
53 - fsl,vmpic-msi
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H A Dfsl,ls-msi.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,ls-msi.yaml#
7 title: Freescale Layerscape SCFG PCIe MSI controller
15 Each PCIe node needs to have property msi-parent that points to
16 MSI controller node
24 - fsl,ls1012a-msi
25 - fsl,ls1021a-msi
26 - fsl,ls1043a-msi
27 - fsl,ls1043a-v1.1-msi
28 - fsl,ls1046a-msi
33 '#msi-cells':
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H A Dsophgo,sg2042-msi.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/sophgo,sg2042-msi.yaml#
7 title: Sophgo SG2042 MSI Controller
14 PCIe MSI to PLIC interrupts.
17 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
22 - sophgo,sg2042-msi
23 - sophgo,sg2044-msi
28 - description: msi doorbell address
35 msi-controller: true
37 msi-ranges:
40 "#msi-cells":
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H A Dloongson,pch-msi.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-msi.yaml#
7 title: Loongson PCH MSI Controller
14 transforming interrupts from PCIe MSI into HyperTransport vectorized
19 const: loongson,pch-msi-1.0
24 loongson,msi-base-vec:
27 to PCH MSI.
32 loongson,msi-num-vecs:
35 to PCH MSI.
40 msi-controller: true
45 - msi-controller
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H A Dfsl,ls-scfg-msi.txt1 * Freescale Layerscape SCFG PCIe MSI controller
5 - compatible: should be "fsl,<soc-name>-msi" to identify
6 Layerscape PCIe MSI controller block such as:
7 "fsl,ls1021a-msi"
8 "fsl,ls1043a-msi"
9 "fsl,ls1046a-msi"
10 "fsl,ls1043a-v1.1-msi"
11 "fsl,ls1012a-msi"
12 - msi-controller: indicates that this is a PCIe MSI controller node
20 Each PCIe node needs to have property msi-parent that points to
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H A Dfsl,mu-msi.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,mu-msi.yaml#
7 title: Freescale/NXP i.MX Messaging Unit (MU) work as msi controller
25 MU can work as msi interrupt controller to do doorbell
28 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
33 - fsl,imx6sx-mu-msi
34 - fsl,imx7ulp-mu-msi
35 - fsl,imx8ulp-mu-msi
36 - fsl,imx8ulp-mu-msi-s4
65 msi-controller: true
67 "#msi-cells":
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H A Dmsi-controller.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/msi-controller.yaml#
7 title: MSI controller
13 An MSI controller signals interrupts to a CPU when a write is made
14 to an MMIO address by some master. An MSI controller may feature a
18 "#msi-cells":
20 The number of cells in an msi-specifier, required if not zero.
26 The meaning of the msi-specifier is defined by the device tree
27 binding of the specific MSI controller.
30 msi-controller:
32 Identifies the node as an MSI controller.
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H A Dal,alpine-msix.yaml21 msi-controller: true
23 al,msi-base-spi:
24 description: SPI base of the MSI frame
27 al,msi-num-spis:
28 description: number of SPIs assigned to the MSI frame, relative to SPI0
34 - msi-controller
35 - al,msi-base-spi
36 - al,msi-num-spis
42 msi-controller@fbe00000 {
46 msi-controller;
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H A Dbrcm,bcm2712-msix.yaml7 title: Broadcom bcm2712 MSI-X Interrupt Peripheral support
15 external MSI-X controller for PCIe root complex.
18 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
29 "#msi-cells":
32 brcm,msi-offset:
34 description: Shift the allocated MSI's.
41 - msi-controller
42 - msi-ranges
52 msi-controller@1000130000 {
56 msi-controller;
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H A Darm,gic-v3.yaml115 msi-controller:
181 mbi-ranges: [ msi-controller ]
182 msi-controller: [ mbi-ranges ]
191 # msi-controller is preferred, but allow other names
192 "^(msi-controller|gic-its|interrupt-controller)@[0-9a-f]+$":
196 used to route Message Signalled Interrupts (MSI) to the CPUs.
207 msi-controller: true
209 "#msi-cells":
211 The single msi-cell is the DeviceID of the device which will generate
212 the MSI.
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H A Dal,alpine-msix.txt3 See arm,gic-v3.txt for SPI and MSI definitions.
10 - msi-controller: identifies the node as an PCI Message Signaled Interrupt
12 - al,msi-base-spi: SPI base of the MSI frame
13 - al,msi-num-spis: number of SPIs assigned to the MSI frame, relative to SPI0
22 msi-controller;
23 al,msi-base-spi = <160>;
24 al,msi-num-spis = <160>;
H A Driscv,imsics.yaml7 title: RISC-V Incoming MSI Controller (IMSIC)
14 MSI controller (IMSIC) for handling MSIs in a RISC-V platform. The RISC-V
32 RISC-V platform. The MSI target address of a IMSIC interrupt file at given
44 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
64 msi-controller: true
66 "#msi-cells":
99 Number of guest index bits in the MSI target address.
105 Number of HART index bits in the MSI target address. When not
113 Number of group index bits in the MSI target address.
122 MSI target address.
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/freebsd/sys/contrib/device-tree/Bindings/powerpc/fsl/
H A Dmsi-pic.txt1 * Freescale MSI interrupt controller
5 The first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
6 etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" or
7 "fsl,mpic-msi-v4.3" depending on the parent type and version. If mpic
8 version is 4.3, the number of MSI registers is increased to 16, MSIIR1 is
9 provided to access these 16 registers, and compatible "fsl,mpic-msi-v4.3"
17 region must be added because different MSI group has different MSIIR1 offset.
21 be set as edge sensitive. If msi-available-ranges is present, only
25 - msi-available-ranges: use <start count> style section to define which
26 msi interrupt can be used in the 256 msi interrupts. This property is
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/freebsd/crypto/krb5/src/windows/installer/wix/
H A Dmsi-deployment-guide.txt4 MSI Deployment Guide
36 Beginning with "Kerberos for Windows" version 2.6.5, a MSI installer
42 customize the MSI package for a particular organization. Although
51 The information in this document applies to MSI packages
53 onwards or MSI packages built from corresponding source
58 software for editing the MSI database tables and generating the
59 transform from the modified MSI package. ORCA.EXE and MSITRAN.EXE
63 For reference, the schema for the MSI package is based on
64 SCHEMA.MSI distributed with the Platform SDK.
68 http://msdn.microsoft.com/library/en-us/msi/setup/windows_installer_start_page.asp
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/freebsd/share/man/man9/
H A Dpci.9468 Read the MSI routing ID.
469 This is needed by some interrupt controllers to route MSI and MSI-X interrupts.
850 .Pq MSI
853 .Pq MSI-X
859 MSI and MSI-X interrupts are available to PCI devices as one or more
862 A driver must ask the PCI bus to allocate MSI or MSI-X interrupts
867 before it can use MSI or MSI-X
872 resource if MSI or MSI-X interrupts have been allocated,
873 and attempts to allocate MSI or MSI-X interrupts will fail if the
877 A driver is only allowed to use either MSI or MSI-X,
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/freebsd/sys/contrib/device-tree/Bindings/misc/
H A Dfsl,qoriq-mc.txt31 The MSI writes are accompanied by sideband data which is derived from the ICID.
32 The msi-map property is used to associate the devices with both the ITS
35 For generic MSI bindings, see
36 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
127 - msi-map: Maps an ICID to a GIC ITS and associated msi-specifier
131 (icid-base,gic-its,msi-base,length).
134 associated with the listed GIC ITS, with the msi-specifier
135 (i - icid-base + msi-base).
139 - msi-parent
141 Definition: Describes the MSI controller node handling message
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H A Dfsl,qoriq-mc.yaml41 The MSI writes are accompanied by sideband data which is derived from the ICID.
42 The msi-map property is used to associate the devices with both the ITS
45 For generic MSI bindings, see
46 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
102 msi-map:
104 Maps an ICID to a GIC ITS and associated msi-specifier
108 (icid-base,gic-its,msi-base,length).
111 associated with the listed GIC ITS, with the msi-specifier
112 (i - icid-base + msi-base).
114 msi-parent:
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