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/linux/drivers/pci/msi/
H A Dapi.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCI MSI/MSI-X — Exported APIs for device drivers
5 * Copyright (C) 2003-2004 Intel
14 #include "msi.h"
17 * pci_enable_msi() - Enable MSI interrupt mode on device
20 * Legacy device driver API to enable MSI interrupts mode on device and
22 * Linux IRQ will be saved at @dev->irq. The driver must invoke
40 * pci_disable_msi() - Disable MSI interrupt mode on device
43 * Legacy device driver API to disable MSI interrupt mode on device,
45 * The PCI device Linux IRQ (@dev->irq) is restored to its default
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H A Dmsi.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
16 #include "msi.h"
21 * pci_msi_supported - check whether MSI may be enabled on a device
22 * @dev: pointer to the pci_dev data structure of MSI device function
26 * to determine if MSI/-X are supported for the device. If MSI/-X is
33 /* MSI must be globally enabled and supported by the device */ in pci_msi_supported()
37 if (!dev || dev->no_msi) in pci_msi_supported()
49 * Any bridge which does NOT route MSI transactions from its in pci_msi_supported()
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/linux/include/linux/
H A Dmsi.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * This header file contains MSI data structures and functions which are
8 * - Interrupt core code
9 * - PCI/MSI core code
10 * - MSI interrupt domain implementations
11 * - IOMMU, low level VFIO, NTB and other justified exceptions
12 * dealing with low level MSI details.
15 * especially storing MSI descriptor pointers in random code is considered
26 #include <asm/msi.h>
52 * msi_msg - Representation of a MSI message
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H A Dpci-epc.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 #include <linux/pci-epf.h>
17 UNKNOWN_INTERFACE = -1,
36 * struct pci_epc_map - information about EPC memory for mapping a RC PCI
65 * struct pci_epc_ops - set of function pointers for performing EPC operations
74 * @set_msi: ops to set the requested number of MSI interrupts in the MSI
76 * @get_msi: ops to get the number of MSI interrupts allocated by the RC from
77 * the MSI capability register
78 * @set_msix: ops to set the requested number of MSI-X interrupts in the
79 * MSI-X capability register
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/linux/drivers/pci/controller/
H A Dpci-xgene-msi.c1 // SPDX-License-Identifier: GPL-2.0+
3 * APM X-Gene MSI Driver
14 #include <linux/msi.h>
16 #include <linux/irqchip/irq-msi-lib.h>
49 * X-Gene v1 has 16 frames of MSI termination registers MSInIRx, where n is
50 * frame number (0..15), x is index of registers in each frame (0..7). Each
54 * Each register supports 16 MSI vectors (0..15) to generate interrupts. A
60 * Additionally, each MSI termination frame has 1 MSIINTn register (n is
61 * 0..15) to indicate the MSI pending status caused by any of its 8
66 * There is one GIC IRQ assigned for each MSI termination frame, 16 in
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H A Dpcie-rcar-host.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe driver for Renesas R-Car SoCs
4 * Copyright (C) 2014-2020 Renesas Electronics Europe Ltd
7 * arch/sh/drivers/pci/pcie-sh7786.c
8 * arch/sh/drivers/pci/ops-sh7786.c
9 * Copyright (C) 2009 - 2011 Paul Mundt
17 #include <linux/clk-provider.h>
21 #include <linux/irqchip/irq-msi-lib.h>
26 #include <linux/msi.h>
36 #include "pcie-rcar.h"
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
30 tristate "Altera PCIe MSI feature"
35 Say Y here if you want PCIe MSI support for the Altera FPGA.
36 This MSI driver supports Altera MSI to GIC controller IP.
52 system-on-chips, like the Apple M1. This is required for the USB
53 type-A ports, Ethernet, Wi-Fi, and Bluetooth.
101 bool "Broadcom iProc PCIe MSI support"
107 Say Y here if you want to enable MSI support for Broadcom's iProc
111 bool "Cavium Thunder PCIe controller to off-chip devices"
119 bool "Cavium Thunder ECAM controller to on-chip devices on pass-1.x silicon"
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H A Dpcie-altera-msi.c1 // SPDX-License-Identifier: GPL-2.0
3 * Altera PCIe MSI support
7 * Copyright Altera Corporation (C) 2013-2015. All rights reserved
12 #include <linux/irqchip/irq-msi-lib.h>
16 #include <linux/msi.h>
41 static inline void msi_writel(struct altera_msi *msi, const u32 value, in msi_writel() argument
44 writel_relaxed(value, msi->csr_base + reg); in msi_writel()
47 static inline u32 msi_readl(struct altera_msi *msi, const u32 reg) in msi_readl() argument
49 return readl_relaxed(msi->csr_base + reg); in msi_readl()
55 struct altera_msi *msi; in altera_msi_isr() local
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H A Dpcie-xilinx-dma-pl.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/irqchip/irq-msi-lib.h>
14 #include <linux/msi.h>
19 #include "pcie-xilinx-common.h"
36 #define IMR(x) BIT(XILINX_PCIE_INTR_ ##x) argument
47 IMR(MSI) | \
77 /* Number of MSI IRQs */
86 * struct xilinx_pl_dma_variant - PL DMA PCIe variant information
102 * struct pl_dma_pcie - PCIe port information
112 * @msi: MSI information
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/linux/Documentation/PCI/endpoint/
H A Dpci-ntb-function.rst1 .. SPDX-License-Identifier: GPL-2.0
9 PCI Non-Transparent Bridges (NTB) allow two host systems to communicate
26 .. code-block:: text
28 +-------------+ +-------------+
32 +------^------+ +------^------+
35 +---------|-------------------------------------------------|---------+
36 | +------v------+ +------v------+ |
40 | | <-----------------------------------> | |
45 | +-------------+ +-------------+ |
46 +---------------------------------------------------------------------+
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H A Dpci-test-function.rst1 .. SPDX-License-Identifier: GPL-2.0
11 However with the addition of EP-core in linux kernel, it is possible
45 Bit 1 raise MSI IRQ
46 Bit 2 raise MSI-X IRQ
82 This register contains the interrupt type (Legacy/MSI) triggered
83 for the READ/WRITE/COPY and raise IRQ (Legacy/MSI) commands.
89 MSI 1
90 MSI-X 2
101 MSI [1 .. 32]
102 MSI-X [1 .. 2048]
/linux/arch/powerpc/sysdev/
H A Dmpic_u3msi.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright 2006-2007, Michael Ellerman, IBM Corporation.
9 #include <linux/msi.h>
12 #include <asm/ppc-pci.h>
39 .name = "MPIC-U3MSI",
66 for (bus = pdev->bus; bus && bus->self; bus = bus->parent) { in find_ht_magic_addr()
67 pos = pci_find_ht_capability(bus->self, HT_CAPTYPE_MSI_MAPPING); in find_ht_magic_addr()
69 return read_ht_magic_addr(bus->self, pos); in find_ht_magic_addr()
77 struct pci_controller *hose = pci_bus_to_host(pdev->bus); in find_u4_magic_addr()
82 * the MSI number and that triggers the right interrupt, but in find_u4_magic_addr()
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/linux/drivers/pci/controller/mobiveil/
H A Dpcie-mobiveil-host.c1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright 2019-2020 NXP
15 #include <linux/irqchip/irq-msi-lib.h>
20 #include <linux/msi.h>
26 #include "pcie-mobiveil.h"
38 if ((bus->primary == to_pci_host_bridge(bus->bridge)->busnr) && (PCI_SLOT(devfn) > 0)) in mobiveil_pcie_valid_device()
45 * mobiveil_pcie_map_bus - routine to get the configuration base of either
51 struct mobiveil_pcie *pcie = bus->sysdata; in mobiveil_pcie_map_bus()
52 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_map_bus()
60 return pcie->csr_axi_slave_base + where; in mobiveil_pcie_map_bus()
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/linux/drivers/xen/xen-pciback/
H A Dpciback_ops.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Backend Operations - respond to PCI requests from Frontend
35 if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) in xen_pcibk_control_isr()
39 dev_data->enable_intx = 0; in xen_pcibk_control_isr()
40 dev_data->ack_intr = 0; in xen_pcibk_control_isr()
42 enable = dev_data->enable_intx; in xen_pcibk_control_isr()
45 if (!enable && !dev_data->isr_on) in xen_pcibk_control_isr()
49 * b/c when device transitions to MSI, the dev->irq is in xen_pcibk_control_isr()
50 * overwritten with the MSI vector. in xen_pcibk_control_isr()
53 dev_data->irq = dev->irq; in xen_pcibk_control_isr()
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/linux/arch/powerpc/platforms/pasemi/
H A Dmsi.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Copyright 2006-2007, Michael Ellerman, IBM Corporation.
13 #include <linux/msi.h>
16 #include <asm/ppc-pci.h>
23 * needs more than 32 MSI's down the road we'll have to rethink this,
36 pr_debug("mpic_pasemi_msi_mask_irq %d\n", data->irq); in mpic_pasemi_msi_mask_irq()
43 pr_debug("mpic_pasemi_msi_unmask_irq %d\n", data->irq); in mpic_pasemi_msi_unmask_irq()
55 .name = "PASEMI-MSI",
65 msi_for_each_desc(entry, &pdev->dev, MSI_DESC_ASSOCIATED) { in pasemi_msi_teardown_msi_irqs()
66 hwirq = virq_to_hw(entry->irq); in pasemi_msi_teardown_msi_irqs()
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/linux/drivers/platform/x86/
H A Dmsi-wmi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MSI WMI hotkeys
7 * Most stuff taken over from hp-wmi
14 #include <linux/input/sparse-keymap.h>
22 MODULE_DESCRIPTION("MSI laptop WMI hotkeys driver");
25 #define DRV_NAME "msi-wmi"
27 #define MSIWMI_BIOS_GUID "551A1F84-FBDD-4125-91DB-3EA8F44F1D45"
28 #define MSIWMI_MSI_EVENT_GUID "B6F3EEF2-3D2F-49DC-9DE3-85BCE18C62F2"
29 #define MSIWMI_WIND_EVENT_GUID "5B3CC38A-40D9-7245-8AE6-1145B751BE3F"
36 /* Generic MSI keys (not present on MSI Wind) */
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/linux/drivers/irqchip/
H A Dirq-bcm2712-mip.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/msi.h>
14 #include <linux/irqchip/irq-msi-lib.h>
30 * struct mip_priv - MSI-X interrupt controller data
33 * @msg_addr: PCIe MSI-X address
34 * @msi_base: MSI base
36 * @msi_offset: MSI offset
57 msg->address_hi = upper_32_bits(mip->msg_addr); in mip_compose_msi_msg()
58 msg->address_lo = lower_32_bits(mip->msg_addr); in mip_compose_msi_msg()
59 msg->data = d->hwirq; in mip_compose_msi_msg()
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H A Dirq-gic-v2m.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * ARM GIC v2m MSI(-X) support
21 #include <linux/msi.h>
26 #include <linux/irqchip/arm-gic.h>
27 #include <linux/irqchip/arm-gic-common.h>
29 #include <linux/irqchip/irq-msi-lib.h>
34 * [25:16] lowest SPI assigned to MSI
36 * [9:0] Numer of SPIs assigned to MSI
47 #define V2M_MSI_TYPER_BASE_SPI(x) \ argument
48 (((x) >> V2M_MSI_TYPER_BASE_SHIFT) & V2M_MSI_TYPER_BASE_MASK)
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/linux/arch/mips/pci/
H A Dmsi-octeon.c6 * Copyright (C) 2005-2009, 2010 Cavium Networks
10 #include <linux/msi.h>
15 #include <asm/octeon/cvmx-npi-defs.h>
16 #include <asm/octeon/cvmx-pci-defs.h>
17 #include <asm/octeon/cvmx-npei-defs.h>
18 #include <asm/octeon/cvmx-sli-defs.h>
19 #include <asm/octeon/cvmx-pexp-defs.h>
20 #include <asm/octeon/pci-octeon.h>
23 * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is
31 * is used so we can disable all of the MSI interrupts when a device
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/linux/Documentation/misc-devices/
H A Dpci-endpoint-test.rst1 .. SPDX-License-Identifier: GPL-2.0
17 #) raise MSI IRQ
18 #) raise MSI-X IRQ
23 This misc driver creates /dev/pci-endpoint-test.<num> for every
28 -----
36 Tests message signalled interrupts. The MSI number
39 Tests message signalled interrupts. The MSI-X number
43 should be passed as argument (0: Legacy, 1:MSI, 2:MSI-X).
56 .. [1] Documentation/PCI/endpoint/function/binding/pci-test.rst
/linux/Documentation/PCI/
H A Dpci.rst1 .. SPDX-License-Identifier: GPL-2.0
7 :Authors: - Martin Mares <mj@ucw.cz>
8 - Grant Grundler <grundler@parisc-linux.org>
11 Since each CPU architecture implements different chip-sets and PCI devices
18 by Jonathan Corbet, Alessandro Rubini, and Greg Kroah-Hartman.
26 "Linux PCI" <linux-pci@atrey.karlin.mff.cuni.cz> mailing list.
38 supporting hot-pluggable PCI, CardBus, and Express-Card in a single driver].
45 - Enable the device
46 - Request MMIO/IOP resources
47 - Set the DMA mask size (for both coherent and streaming DMA)
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/linux/Documentation/networking/device_drivers/ethernet/neterion/
H A Ds2io.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Neterion's (Formerly S2io) Xframe I/II PCI-X 10GbE driver
7 Release notes for Neterion's (Formerly S2io) Xframe I/II PCI-X 10GbE driver.
10 - 1. Introduction
11 - 2. Identifying the adapter/interface
12 - 3. Features supported
13 - 4. Command line parameters
14 - 5. Performance suggestions
15 - 6. Available Downloads
20 This Linux driver supports Neterion's Xframe I PCI-X 1.0 and
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/linux/drivers/pci/pcie/
H A Dportdrv.c1 // SPDX-License-Identifier: GPL-2.0
27 * be one of the first 32 MSI-X entries. Per PCI r3.0, sec 6.8.3.1, MSI
32 #define get_descriptor_id(type, service) (((type - 4) << 8) | service)
41 * release_pcie_device - free PCI Express port service device structure
54 * services are enabled in "mask". Return the number of MSI/MSI-X vectors
65 * the MSI-X table entry or the MSI offset between the base Message in pcie_message_numbers()
81 pos = dev->aer_cap; in pcie_message_numbers()
105 * pcie_port_enable_irq_vec - try to set up MSI-X or MSI as interrupt mode
118 /* Allocate the maximum possible number of MSI/MSI-X vectors */ in pcie_port_enable_irq_vec()
128 return -EIO; in pcie_port_enable_irq_vec()
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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dmarvell,mpic.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/marvell,mpic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell Armada 370, 375, 38x, 39x, XP Interrupt Controller
10 - Marek Behún <kabel@kernel.org>
13 The top-level interrupt controller on Marvell Armada 370 and XP. On these
14 platforms it also provides inter-processor interrupts.
16 On Marvell Armada 375, 38x and 39x this controller is wired under ARM GIC.
18 Provides MSI handling for the PCIe controllers.
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/linux/drivers/pci/controller/plda/
H A Dpcie-microchip-host.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2018 - 2020 Microchip Corporation. All rights reserved.
18 #include <linux/msi.h>
21 #include <linux/pci-ecam.h>
26 #include "../pci-host-common.h"
27 #include "pcie-plda.h"
88 /* PCIe Config space MSI capability structure */
123 #define PCIE_EVENT_CAUSE(x, s) \ argument
124 [EVENT_PCIE_ ## x] = { __stringify(x), s }
126 #define SEC_ERROR_CAUSE(x, s) \ argument
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