| /linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | msi.txt | 1 This document describes the generic device tree binding for MSI controllers and
9 those busses to the MSI controllers which they are capable of using,
14 - The doorbell (the MMIO address written to).
17 they can address. An MSI controller may feature a number of doorbells.
19 - The payload (the value written to the doorbell).
22 MSI controllers may have restrictions on permitted payloads.
24 - Sideband information accompanying the write.
28 MSI controller and device rather than a property of either in isolation).
31 MSI controllers:
34 An MSI controller signals interrupts to a CPU when a write is made to an MMIO
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| /linux/Documentation/devicetree/bindings/pci/ |
| H A D | brcm,stb-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/brcm,stb-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jim Quinlan <james.quinlan@broadcom.com>
15 - enum:
16 - brcm,bcm2711-pcie # The Raspberry Pi 4
17 - brcm,bcm4908-pcie
18 - brcm,bcm7211-pcie # Broadcom STB version of RPi4
19 - brcm,bcm7216-pcie # Broadcom 7216 Arm
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| H A D | baikal,bt1-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/baikal,bt1-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Baikal-T1 PCIe Root Port Controller
10 - Serge Semin <fancer.lancer@gmail.com>
13 Embedded into Baikal-T1 SoC Root Complex controller with a single port
14 activated. It's based on the DWC RC PCIe v4.60a IP-core, which is configured
15 to have just a single Root Port function and is capable of establishing the
18 performed by software. There four in- and four outbound iATU regions
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| H A D | xlnx,nwl-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/xlnx,nwl-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thippeswamy Havalige <thippeswamy.havalige@amd.com>
13 - $ref: /schemas/pci/pci-host-bridge.yaml#
14 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
18 const: xlnx,nwl-pcie-2.11
22 - description: PCIe bridge registers location.
23 - description: PCIe Controller registers location.
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| H A D | snps,dw-pcie-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
23 Interface - DBI. In accordance with the reference manual the register
24 configuration space belongs to the Configuration-Dependent Module (CDM)
25 and is split up into several sub-parts Standard PCIe configuration
26 space, Port Logic Registers (PL), Shadow Config-space Registers,
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| H A D | snps,dw-pcie-ep.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Endpoint controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie-ep
23 - compatible
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| /linux/Documentation/devicetree/bindings/dma/ |
| H A D | marvell,xor-v2.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/dma/marvell,xor-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
15 - const: marvell,xor-v2
16 - items:
17 - enum:
18 - marvell,armada-7k-xor
19 - const: marvell,xor-v2
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| /linux/drivers/ata/ |
| H A D | ahci.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * ahci.h - Common AHCI SATA definitions and declarations
6 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2004-2005 Red Hat, Inc.
12 * as Documentation/driver-api/libata.rst
80 HOST_RESET = BIT(0), /* reset controller; self-clear */
82 HOST_MRSM = BIT(2), /* MSI Revert to Single Message */
89 HOST_CAP_PART = BIT(13), /* Partial state capable */
90 HOST_CAP_SSC = BIT(14), /* Slumber state capable */
92 HOST_CAP_FBS = BIT(16), /* FIS-based switching support */
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| /linux/drivers/pci/msi/ |
| H A D | msi.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
15 #include "msi.h"
21 * pci_msi_supported - check whether MSI may be enabled on a device
22 * @dev: pointer to the pci_dev data structure of MSI device function
26 * to determine if MSI/-X are supported for the device. If MSI/-X is
33 /* MSI must be globally enabled and supported by the device */ in pci_msi_supported()
37 if (!dev || dev->no_msi) in pci_msi_supported()
49 * Any bridge which does NOT route MSI transactions from its in pci_msi_supported()
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| /linux/drivers/pci/controller/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
25 tristate "Altera PCIe MSI feature"
29 Say Y here if you want PCIe MSI support for the Altera FPGA.
30 This MSI driver supports Altera MSI to GIC controller IP.
45 system-on-chips, like the Apple M1. This is required for the USB
46 type-A ports, Ethernet, Wi-Fi, and Bluetooth.
93 bool "Broadcom iProc PCIe MSI support"
98 Say Y here if you want to enable MSI support for Broadcom's iProc
102 bool "Cavium Thunder PCIe controller to off-chip devices"
110 bool "Cavium Thunder ECAM controller to on-chip devices on pass-1.x silicon"
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| /linux/Documentation/PCI/ |
| H A D | pci.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 :Authors: - Martin Mares <mj@ucw.cz>
8 - Grant Grundler <grundler@parisc-linux.org>
11 Since each CPU architecture implements different chip-sets and PCI devices
18 by Jonathan Corbet, Alessandro Rubini, and Greg Kroah-Hartman.
26 "Linux PCI" <linux-pci@atrey.karlin.mff.cuni.cz> mailing list.
38 supporting hot-pluggable PCI, CardBus, and Express-Card in a single driver].
45 - Enable the device
46 - Request MMIO/IOP resources
47 - Set the DMA mask size (for both coherent and streaming DMA)
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| H A D | pci-error-recovery.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 :Authors: - Linas Vepstas <linasvepstas@gmail.com>
9 - Richard Lary <rlary@us.ibm.com>
10 - Mike Mason <mmlnx@us.ibm.com>
16 chipsets are able to deal with these errors; these include PCI-E chipsets,
17 and the PCI-host bridges found on IBM Power4, Power5 and Power6-based
32 including multiple instances of a device driver on multi-function
34 waiting for some i/o-space register to change, when it never will.
39 is forced by the need to handle multi-function devices, that is,
42 of reset it desires, the choices being a simple re-enabling of I/O
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| /linux/arch/arm64/boot/dts/freescale/ |
| H A D | fsl-ls1043a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1043A family SoC.
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/thermal/thermal.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/gpio/gpio.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
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| H A D | fsl-ls1046a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1046A family SoC.
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/gpio/gpio.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
37 #address-cells = <1>;
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| /linux/include/xen/interface/ |
| H A D | physdev.h | 1 /* SPDX-License-Identifier: MIT */
10 * @args == Operation-specific extra arguments (NULL if none).
14 * Notify end-of-interrupt (EOI) for the specified IRQ.
75 * Set the current VCPU's I/O-port permissions bitmap.
86 * Read or write an IO-APIC register.
127 /* IN - high 16 bits hold segment for ..._MSI_SEG and ..._MULTI_MSI */
132 * - For MSI-X contains entry number.
133 * - For MSI with ..._MULTI_MSI contains number of vectors.
135 * - Number of vectors allocated.
255 * MSI-X capable devices won't (prepare) or may (release) change.
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| /linux/include/linux/ |
| H A D | msi.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
6 * This header file contains MSI data structures and functions which are
8 * - Interrupt core code
9 * - PCI/MSI core code
10 * - MSI interrupt domain implementations
11 * - IOMMU, low level VFIO, NTB and other justified exceptions
12 * dealing with low level MSI details.
15 * especially storing MSI descriptor pointers in random code is considered
26 #include <asm/msi.h>
52 * msi_msg - Representation of a MSI message
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| /linux/Documentation/arch/x86/ |
| H A D | sva.rst | 1 .. SPDX-License-Identifier: GPL-2.0
19 application page-faults. For more information please refer to the PCIe
34 Unlike Single Root I/O Virtualization (SR-IOV), Scalable IOV (SIOV) permits
40 ID (PASID), which is a 20-bit number defined by the PCIe SIG.
43 IOMMU to track I/O on a per-PASID granularity in addition to using the PCIe
55 ENQCMD works with non-posted semantics and carries a status back if the
67 A new thread-scoped MSR (IA32_PASID) provides the connection between
69 accesses an SVA-capable device, this MSR is initialized with a newly
70 allocated PASID. The driver for the device calls an IOMMU-specific API
71 that sets up the routing for DMA and page-requests.
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| /linux/drivers/net/ethernet/chelsio/cxgb3/ |
| H A D | cxgb3_main.c | 2 * Copyright (c) 2003-2008 Chelsio, Inc. All rights reserved.
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
38 #include <linux/dma-mapping.h>
77 #define PORT_MASK ((1 << MAX_NPORTS) - 1)
99 CH_DEVICE(0x35, 6), /* T3C20-derived T3C10 */
100 CH_DEVICE(0x36, 3), /* S320E-CR */
101 CH_DEVICE(0x37, 7), /* N320E-G2 */
117 * order MSI-X, MSI, legacy pin interrupts. This parameter determines which
120 * msi = 2: choose from among all three options
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| /linux/drivers/gpu/drm/xe/ |
| H A D | xe_device_types.h | 1 /* SPDX-License-Identifier: MIT */
3 * Copyright © 2022-2023 Intel Corporation
40 #define GRAPHICS_VER(xe) ((xe)->info.graphics_verx100 / 100)
41 #define MEDIA_VER(xe) ((xe)->info.media_verx100 / 100)
42 #define GRAPHICS_VERx100(xe) ((xe)->info.graphics_verx100)
43 #define MEDIA_VERx100(xe) ((xe)->info.media_verx100)
44 #define IS_DGFX(xe) ((xe)->info.is_dgfx)
55 ((_xe)->info.platform == (_platform) && \
56 (_xe)->info.step.graphics >= (min_step) && \
57 (_xe)->info.step.graphics < (max_step))
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| /linux/drivers/net/ethernet/netronome/nfp/ |
| H A D | nfp_net_ctrl.h | 1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2 /* Copyright (C) 2015-2018 Netronome Systems, Inc. */
17 /* 64-bit per app capabilities */
23 * THB-350, 32k needs to be reserved.
61 /* Hash type pre-pended when a RSS hash was computed */
80 /* Read/Write config words (0x0000 - 0x002c)
87 * %NFP_NET_CFG_EXN: MSI-X table entry for exceptions
88 * %NFP_NET_CFG_LSC: MSI-X table entry for link state changes
92 * - define Error details in UPDATE
108 #define NFP_NET_CFG_CTRL_RXQINQ (0x1 << 13) /* Enable S-tag strip */
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| /linux/kernel/irq/ |
| H A D | msi.c | 1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/msi.h>
25 * struct msi_device_data - MSI per device data
26 * @properties: MSI properties which are interesting to drivers
27 * @mutex: Mutex protecting the MSI descriptor store
28 * @__domains: Internal data for per device MSI domains
39 * struct msi_ctrl - MSI internal management control structure
44 * than the range due to PCI/multi-MSI.
54 #define MSI_XA_MAX_INDEX (ULONG_MAX - 1)
64 * msi_alloc_desc - Allocate an initialized msi_desc
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| /linux/drivers/net/ethernet/sfc/ |
| H A D | efx_channels.c | 1 // SPDX-License-Identifier: GPL-2.0-only
24 * 0 => MSI-X
25 * 1 => MSI
30 /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS),
34 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt.
62 netif_warn(efx, probe, efx->net_dev, in count_online_cores()
70 cpumask_of_pcibus(efx->pci_dev->bus)); in count_online_cores()
98 netif_cond_dbg(efx, probe, efx->net_dev, !rss_cpus, warn, in efx_wanted_parallelism()
108 if (efx->type->sriov_wanted) { in efx_wanted_parallelism()
109 if (efx->type->sriov_wanted(efx) && efx_vf_size(efx) > 1 && in efx_wanted_parallelism()
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| /linux/drivers/net/ethernet/sfc/siena/ |
| H A D | efx_channels.c | 1 // SPDX-License-Identifier: GPL-2.0-only
24 * 0 => MSI-X
25 * 1 => MSI
30 /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS),
34 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt.
62 netif_warn(efx, probe, efx->net_dev, in count_online_cores()
70 cpumask_of_pcibus(efx->pci_dev->bus)); in count_online_cores()
98 netif_cond_dbg(efx, probe, efx->net_dev, !efx_siena_rss_cpus, in efx_wanted_parallelism()
109 if (efx->type->sriov_wanted) { in efx_wanted_parallelism()
110 if (efx->type->sriov_wanted(efx) && efx_vf_size(efx) > 1 && in efx_wanted_parallelism()
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| /linux/arch/arm/boot/dts/nxp/ls/ |
| H A D | ls1021a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <2>;
11 #size-cells = <2>;
12 interrupt-parent = <&gic>;
30 #address-cells = <1>;
31 #size-cells = <0>;
34 compatible = "arm,cortex-a7";
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| /linux/drivers/iommu/ |
| H A D | virtio-iommu.c | 1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/dma-map-ops.h>
25 #include "dma-iommu.h"
105 struct virtio_iommu_req_tail *tail = buf + len - sizeof(*tail); in viommu_get_req_errno()
107 switch (tail->status) { in viommu_get_req_errno()
111 return -ENOSYS; in viommu_get_req_errno()
113 return -EINVAL; in viommu_get_req_errno()
115 return -ERANGE; in viommu_get_req_errno()
117 return -ENOENT; in viommu_get_req_errno()
119 return -EFAULT; in viommu_get_req_errno()
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