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Searched full:mscr (Results 1 – 6 of 6) sorted by relevance

/linux/Documentation/devicetree/bindings/pinctrl/
H A Dnxp,s32g2-siul2-pinctrl.yaml20 Every SIUL2 region has multiple register types, and here only MSCR and
33 A list of MSCR/IMCR register regions to be reserved.
34 - MSCR (Multiplexed Signal Configuration Register)
35 An MSCR register can configure the associated pin as either a GPIO pin
41 - description: MSCR registers group 0 in SIUL2_0
42 - description: MSCR registers group 1 in SIUL2_1
43 - description: MSCR registers group 2 in SIUL2_1
/linux/drivers/edac/
H A Dcpc925_edac.c136 * Memory Scrub Control Register (MSCR)
867 u32 mscr; in cpc925_get_sdram_scrub_rate() local
870 mscr = __raw_readl(pdata->vbase + REG_MSCR_OFFSET); in cpc925_get_sdram_scrub_rate()
871 si = (mscr & MSCR_SI_MASK) >> MSCR_SI_SHIFT; in cpc925_get_sdram_scrub_rate()
873 edac_dbg(0, "Mem Scrub Ctrl Register 0x%x\n", mscr); in cpc925_get_sdram_scrub_rate()
875 if (((mscr & MSCR_SCRUB_MOD_MASK) != MSCR_BACKGR_SCRUB) || in cpc925_get_sdram_scrub_rate()
/linux/drivers/net/ethernet/dlink/
H A Ddl2k.c1491 __u16 mscr; in mii_get_media() local
1507 mscr = mii_read (dev, phy_addr, MII_CTRL1000); in mii_get_media()
1509 if (mscr & ADVERTISE_1000FULL && mssr & LPA_1000FULL) { in mii_get_media()
1513 } else if (mscr & ADVERTISE_1000HALF && mssr & LPA_1000HALF) { in mii_get_media()
1651 mscr = mii_read (dev, phy_addr, MII_CTRL1000); in mii_set_media()
1652 mscr |= MII_MSCR_CFG_ENABLE; in mii_set_media()
1653 mscr &= ~MII_MSCR_CFG_VALUE = 0; in mii_set_media()
/linux/drivers/pinctrl/nxp/
H A Dpinctrl-s32g2.c766 /* MSCR pin ID ranges */
H A Dpinctrl-s32cc.c583 /* If the MSCR configuration has to be written, in s32_pinconf_mscr_write()
/linux/drivers/net/ethernet/freescale/
H A Dfec_main.c2586 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka in fec_enet_mii_init()
2605 /* Clear MMFR to avoid to generate MII event by writing MSCR. in fec_enet_mii_init()
2607 * - writing MSCR: in fec_enet_mii_init()
2608 * - mmfr[31:0]_not_zero & mscr[7:0]_is_zero & in fec_enet_mii_init()
2611 * - mscr[7:0]_not_zero in fec_enet_mii_init()