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/linux/drivers/firmware/xilinx/
H A DKconfig4 menu "Zynq MPSoC Firmware Drivers"
8 bool "Enable Xilinx Zynq MPSoC firmware interface"
20 bool "Enable Xilinx Zynq MPSoC firmware debug APIs"
H A Dzynqmp-debug.h3 * Xilinx Zynq MPSoC Firmware layer
/linux/Documentation/devicetree/bindings/reset/
H A Dxlnx,zynqmp-reset.yaml7 title: Zynq UltraScale+ MPSoC and Versal reset
13 The Zynq UltraScale+ MPSoC and Versal has several different resets.
24 For list of all valid reset indices for Zynq UltraScale+ MPSoC
/linux/Documentation/devicetree/bindings/fpga/
H A Dxlnx,zynqmp-pcap-fpga.yaml7 title: Xilinx Zynq Ultrascale MPSoC FPGA Manager
13 Device Tree Bindings for Zynq Ultrascale MPSoC FPGA Manager.
/linux/Documentation/devicetree/bindings/nvmem/
H A Dxlnx,zynqmp-nvmem.yaml7 title: Zynq UltraScale+ MPSoC Non Volatile Memory interface
10 The ZynqMP MPSoC provides access to the hardware related data
/linux/Documentation/devicetree/bindings/rtc/
H A Dxlnx,zynqmp-rtc.yaml7 title: Xilinx Zynq Ultrascale+ MPSoC Real Time Clock
10 RTC controller for the Xilinx Zynq MPSoC Real Time Clock.
/linux/Documentation/driver-api/xilinx/
H A Deemi.rst2 Xilinx Zynq MPSoC EEMI Documentation
5 Xilinx Zynq MPSoC Firmware Interface
/linux/Documentation/devicetree/bindings/firmware/xilinx/
H A Dxlnx,zynqmp-firmware.yaml23 - description: For implementations complying for Zynq Ultrascale+ MPSoC.
67 description: The ZynqMP MPSoC provides access to the hardware related data
/linux/drivers/pmdomain/xilinx/
H A DKconfig4 bool "Enable Zynq MPSoC generic PM domains"
/linux/drivers/clk/zynqmp/
H A DMakefile2 # Zynq Ultrascale+ MPSoC clock specific Makefile
H A Dclk-gate-zynqmp.c3 * Zynq UltraScale+ MPSoC clock controller
H A Dclk-mux-zynqmp.c3 * Zynq UltraScale+ MPSoC mux
H A Dclkc.c3 * Zynq UltraScale+ MPSoC clock controller
675 pr_err("Zynq Ultrascale+ MPSoC clk %s: register failed with %ld\n", in zynqmp_register_clocks()
H A Ddivider.c3 * Zynq UltraScale+ MPSoC Divider support
H A Dpll.c3 * Zynq UltraScale+ MPSoC PLL driver
/linux/Documentation/devicetree/bindings/net/
H A Dcdns,macb.yaml24 - cdns,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC
32 - xlnx,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC
/linux/drivers/soc/xilinx/
H A DKconfig5 bool "Enable Xilinx Zynq MPSoC Power Management driver"
/linux/Documentation/devicetree/bindings/spi/
H A Dspi-zynqmp-qspi.yaml7 title: Xilinx Zynq UltraScale+ MPSoC GQSPI controller
/linux/arch/arm64/boot/dts/xilinx/
H A Dxlnx-zynqmp-clk.h3 * Xilinx Zynq MPSoC Firmware layer
/linux/drivers/rtc/
H A Drtc-zynqmp.c3 * Xilinx Zynq Ultrascale+ MPSoC Real Time Clock Driver
395 MODULE_DESCRIPTION("Xilinx Zynq MPSoC RTC driver");
H A DKconfig1355 tristate "Xilinx Zynq Ultrascale+ MPSoC RTC"
1359 Xilinx Zynq Ultrascale+ MPSoC.
/linux/include/dt-bindings/clock/
H A Dxlnx-zynqmp-clk.h3 * Xilinx Zynq MPSoC Firmware layer
/linux/Documentation/devicetree/bindings/mailbox/
H A Dxlnx,zynqmp-ipi-mailbox.yaml11 messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents. Each IPI
/linux/Documentation/devicetree/bindings/display/xlnx/
H A Dxlnx,zynqmp-dpsub.yaml10 The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale+ MPSoC)
/linux/include/linux/firmware/
H A Dxlnx-zynqmp.h3 * Xilinx Zynq MPSoC Firmware layer

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