Home
last modified time | relevance | path

Searched full:mpcore (Results 1 – 25 of 43) sorted by relevance

12

/freebsd/sys/contrib/device-tree/Bindings/arm/marvell/
H A Darmada-380-mpcore-soc-ctrl.txt1 Marvell Armada 38x CA9 MPcore SoC Controller
6 - compatible: Should be "marvell,armada-380-mpcore-soc-ctrl".
9 datasheet for the CA9 MPcore SoC Control registers
11 mpcore-soc-ctrl@20d20 {
12 compatible = "marvell,armada-380-mpcore-soc-ctrl";
/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dscu.txt3 As part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided
9 - Cortex-A9: see DDI0407E Cortex-A9 MPCore Technical Reference Manual
11 - Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual
13 - ARM11 MPCore: see DDI0360F ARM 11 MPCore Processor Technical Reference
H A Darm,scu.yaml13 As part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided
18 - Cortex-A9: see DDI0407E Cortex-A9 MPCore Technical Reference Manual
20 - Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual
22 - ARM11 MPCore: see DDI0360F ARM 11 MPCore Processor Technical Reference
H A Darm,realview.yaml15 the earlier CPUs such as TrustZone and multicore (MPCore).
32 - description: ARM RealView Platform Baseboard for ARM 11 MPCore
34 multiprocessing with ARM11 using MPCore using symmetric
H A Darm,vexpress-juno.yaml46 in MPCore configuration in a test chip on the core tile. See ARM
58 cores in a MPCore configuration in a test chip on the core tile. See
71 CPU cores and 3 Cortex A7 cores in a big.LITTLE MPCore configuration
/freebsd/sys/arm/arm/
H A Dmpcore_timervar.h31 * This value, passed to arm_tmr_change_frequency() any time before the mpcore
32 * timer device attaches, informs the driver that the mpcore clock frequency can
40 * Inform the mpcore timer driver of a new clock frequency. This can be called
41 * both before and after the mpcore timer driver attaches.
H A Dmpcore_timer.c44 * REF: ARM Cortex-A9 MPCore, Technical Reference Manual (rev. r2p2)
124 .tc_name = "MPCore",
138 {"arm,mpcore-timers", TMR_BOTH}, /* Non-standard, FreeBSD. */
257 * string set to "arm,mpcore-timers".
272 device_set_desc(dev, "ARM MPCore Timers"); in arm_tmr_probe()
346 sc->et.et_name = "MPCore"; in attach_et()
465 * Handle a change in clock frequency. The mpcore timer runs at half the CPU
/freebsd/sys/contrib/device-tree/src/arm/arm/
H A Darm-realview-eb-a9mp.dts27 model = "ARM RealView EB Cortex A9 MPCore";
30 * This is the Cortex A9 MPCore tile used with the
H A Darm-realview-eb-11mp.dts31 * This is the ARM11 MPCore tile (HBI-0146) used with the RealView EB.
35 * qemu-system-arm -M realview-eb-mpcore -smp cpus=4
H A Darm-realview-eb-mp.dtsi28 * This is the common include file for all MPCore variants of the
30 * and Cortex-A9 MPCore.
H A Darm-realview-eb-a9mp-bbrevd.dts27 model = "ARM RealView EB Baseboard Rev D Cortex A9 MPCore";
H A Dvexpress-v2p-ca5s.dts6 * Cortex-A5 MPCore (V2P-CA5s)
/freebsd/sys/contrib/device-tree/Bindings/display/tegra/
H A Dnvidia,tegra20-host1x.yaml241 interrupts = <0 65 0x04>, /* mpcore syncpt */
242 <0 67 0x04>; /* mpcore general */
377 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* mpcore syncpt */
378 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* mpcore general */
/freebsd/sys/arm/conf/
H A DZEDBOARD54 # ARM MPCore timer
H A DNOTES28 device mpcore_timer # ARM MPCore Timer
/freebsd/sys/contrib/device-tree/src/arm/xen/
H A Dxenvm-4.2.dts6 * Cortex-A15 MPCore (V2P-CA15)
/freebsd/sys/dts/arm/
H A Dtegra20.dtsi53 compatible = "arm,mpcore-timers";
H A Dtrimslice.dts67 compatible = "arm,mpcore-timers";
H A Dzynq-7000.dtsi92 compatible = "arm,mpcore-timers";
/freebsd/sys/arm/freescale/imx/
H A Dimx6_ccm.c167 * when a WFI instruction is executed. This lets the MPCore timers and in ccm_attach()
169 * wake you up is an MPCore Private Timer interrupt delivered via GIC. in ccm_attach()
H A Dimx6_machdep.c204 /* Inform the MPCore timer driver that its clock is variable. */ in imx6_attach()
224 * ARMMP covers the interrupt controller, MPCore timers, global timer, and the
/freebsd/sys/contrib/device-tree/Bindings/remoteproc/
H A Dxlnx,zynqmp-r5fss.yaml27 The RPU MPCore can operate in split mode (Dual-processor performance), Safety
/freebsd/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm5301x.dtsi12 mpcore-bus@19000000 {
H A Dbcm53573.dtsi35 mpcore@18310000 {
/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Darmada-39x.dtsi304 mpcore-soc-ctrl@20d20 {
305 compatible = "marvell,armada-380-mpcore-soc-ctrl";

12