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/linux/Documentation/devicetree/bindings/display/bridge/
H A Dps8640.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MIPI DSI to eDP Video Format Converter
10 - Nicolas Boichat <drinkcat@chromium.org>
13 The PS8640 is a low power MIPI-to-eDP video format converter supporting
14 mobile devices with embedded panel resolutions up to 2048 x 1536. The
15 device accepts a single channel of MIPI DSI v1.1, with up to four lanes
16 plus clock, at a transmission rate up to 1.5Gbit/sec per lane. The
17 device outputs eDP v1.4, one or two lanes, at a link rate of up to
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H A Dti,sn65dsi86.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SN65DSI86 DSI to eDP bridge chip
10 - Douglas Anderson <dianders@chromium.org>
13 The Texas Instruments SN65DSI86 bridge takes MIPI DSI in and outputs eDP.
23 enable-gpios:
27 suspend-gpios:
31 no-hpd:
34 Set if the HPD line on the bridge isn't hooked up to anything or is
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/linux/drivers/phy/rockchip/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
10 Enable this to support the Rockchip Display Port PHY.
13 tristate "Rockchip MIPI Synopsys DPHY RX0 driver"
18 Enable this to support the Rockchip MIPI Synopsys DPHY RX0
19 associated to the Rockchip ISP module present in RK3399 SoCs.
21 To compile this driver as a module, choose M here: the module
22 will be called phy-rockchip-dphy-rx0.
29 Enable this to support the Rockchip EMMC PHY.
38 Enable this to support the Rockchip Innosilicon HDMI PHY.
52 tristate "Rockchip Innosilicon MIPI CSI PHY driver"
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/linux/drivers/gpu/drm/bridge/analogix/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
11 ANX6345 is an ultra-low power Full-HD DisplayPort/eDP
14 application processor to eDP or DisplayPort.
24 ANX78XX is an ultra-low power Full-HD SlimPort transmitter
26 the HDMI output of an application processor to MyDP
34 tristate "Analogix Anx7625 MIPI to DP interface support"
43 ANX7625 is an ultra-low power 4K mobile HD transmitter
44 designed for portable devices. It converts MIPI/DPI to
H A Danx7625.c1 // SPDX-License-Identifier: GPL-2.0-only
35 #include <media/v4l2-fwnode.h>
36 #include <sound/hdmi-codec.h>
43 * internal firmware(OCM), to avoid the race condition, AP should access
50 struct device *dev = &client->dev; in i2c_access_workaround()
53 if (client == ctx->last_client) in i2c_access_workaround()
56 ctx->last_client = client; in i2c_access_workaround()
58 if (client == ctx->i2c.tcpc_client) in i2c_access_workaround()
60 else if (client == ctx->i2c.tx_p0_client) in i2c_access_workaround()
62 else if (client == ctx->i2c.tx_p1_client) in i2c_access_workaround()
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/linux/Documentation/devicetree/bindings/arm/tegra/
H A Dnvidia,tegra186-pmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra186-pmc
17 - nvidia,tegra194-pmc
18 - nvidia,tegra234-pmc
19 - nvidia,tegra264-pmc
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/linux/drivers/gpu/drm/bridge/
H A Dti-sn65dsi86.c1 // SPDX-License-Identifier: GPL-2.0
38 #define SN_DEVICE_ID_REGS 0x00 /* up to 0x07 */
116 /* fudge factor required to account for 8b/10b encoding */
134 * struct ti_sn65dsi86 - Platform data for ti-sn65dsi86 driver.
135 * @bridge_aux: AUX-bus sub device for MIPI-to-eDP bridge functionality.
136 * @gpio_aux: AUX-bus sub device for GPIO controller functionality.
137 * @aux_aux: AUX-bus sub device for eDP AUX channel functionality.
138 * @pwm_aux: AUX-bus sub device for PWM controller functionality.
140 * @dev: Pointer to the top level (i2c) device.
146 * @dsi: Our MIPI DSI source.
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/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8186-corsola-starmie.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
7 #include "mt8186-corsola.dtsi"
10 en_pp6000_mipi_disp_150ma: en-pp6000-mipi-disp-150ma {
11 compatible = "regulator-fixed";
12 regulator-name = "en_pp6000_mipi_disp_150ma";
14 enable-active-high;
15 pinctrl-names = "default";
16 pinctrl-0 = <&en_pp6000_mipi_disp_150ma_fixed_pins>;
21 * with 6V module for enabling panel, re-using eDP GPIOs.
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/linux/Documentation/userspace-api/media/mediactl/
H A Dmedia-types.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _media-controller-types:
5 Types and flags used to represent the media graph elements
10 .. _media-entity-functions:
11 .. _MEDIA-ENT-F-UNKNOWN:
12 .. _MEDIA-ENT-F-V4L2-SUBDEV-UNKNOWN:
13 .. _MEDIA-ENT-F-IO-V4L:
14 .. _MEDIA-ENT-F-IO-VBI:
15 .. _MEDIA-ENT-F-IO-SWRADIO:
16 .. _MEDIA-ENT-F-IO-DTV:
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/linux/drivers/clk/sunxi-ng/
H A Dccu-sun9i-a80.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved.
6 #include <linux/clk-provider.h>
21 #include "ccu-sun9i-a80.h"
28 * Neither mainline Linux, U-boot, nor the vendor BSPs use these.
30 * For now we can just model it as a multiplier clock, and force P to /1.
43 .hw.init = CLK_HW_INIT("pll-c0cpux", "osc24M",
57 .hw.init = CLK_HW_INIT("pll-c1cpux", "osc24M",
64 * The Audio PLL has d1, d2 dividers in addition to the usual N, M
79 .hw.init = CLK_HW_INIT("pll-audio", "osc24M",
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H A Dccu-sun55i-a523.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2023-2024 Arm Ltd.
9 #include <linux/clk-provider.h>
14 #include <dt-bindings/clock/sun55i-a523-ccu.h>
15 #include <dt-bindings/reset/sun55i-a523-ccu.h>
33 * .fw_name is the string used in the DT "clock-names" property, used to
54 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-ddr0", osc24M,
74 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-periph0-4x",
80 * Most clock-defining macros expect an *array* of parent clocks, even if
81 * they do not contain a muxer to select between different parents.
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/linux/arch/arm/boot/dts/rockchip/
H A Drk3288.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3288-cru.h>
8 #include <dt-bindings/power/rk3288-power.h>
9 #include <dt-bindings/thermal/thermal.h>
10 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #address-cells = <2>;
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/linux/arch/arm/boot/dts/nvidia/
H A Dtegra124.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra124-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra124-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/tegra124-car.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
9 #include <dt-bindings/soc/tegra-pmc.h>
11 #include "tegra124-peripherals-opp.dtsi"
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/linux/drivers/soc/tegra/
H A Dpmc.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (c) 2018-2024, NVIDIA CORPORATION. All rights reserved.
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
14 #include <linux/arm-smccc.h>
16 #include <linux/clk-provider.h>
18 #include <linux/clk/clk-conf.h>
37 #include <linux/pinctrl/pinconf-generic.h>
57 #include <dt-bindings/interrupt-controller/arm-gic.h>
58 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
59 #include <dt-bindings/gpio/tegra186-gpio.h>
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/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra210.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra210-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra210-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/reset/tegra210-car.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/tegra124-soctherm.h>
10 #include <dt-bindings/soc/tegra-pmc.h>
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H A Dtegra132.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra124-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra124-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
9 #include <dt-bindings/soc/tegra-pmc.h>
11 #include "tegra132-peripherals-opp.dtsi"
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/linux/drivers/gpu/drm/sun4i/
H A Dsun4i_tcon.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
11 #include <linux/media-bus-format.h>
48 drm_connector_list_iter_begin(encoder->dev, &iter); in sun4i_tcon_get_connector()
50 if (connector->encoder == encoder) { in sun4i_tcon_get_connector()
66 return -EINVAL; in sun4i_tcon_get_pixel_depth()
68 info = &connector->display_info; in sun4i_tcon_get_pixel_depth()
69 if (info->num_bus_formats != 1) in sun4i_tcon_get_pixel_depth()
70 return -EINVAL; in sun4i_tcon_get_pixel_depth()
72 switch (info->bus_formats[0]) { in sun4i_tcon_get_pixel_depth()
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/linux/drivers/gpu/drm/
H A Ddrm_framebuffer.c4 * Permission to use, copy, modify, distribute, and sell this software and its
9 * publicity pertaining to distribution of the software without specific,
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
44 * Frame buffers are abstract memory objects that provide a source of pixels to
45 * scanout to a CRTC. Applications explicitly request the creation of frame
47 * handle that can be passed to the KMS CRTC control, plane configuration and
52 * (or a list of memory handles for multi-planar formats) through the
55 * free to use their own backing storage object handles, e.g. vmwgfx directly
56 * exposes special TTM handles to userspace and so expects TTM handles in the
60 * using drm_framebuffer_init() - after calling that function userspace can use
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/linux/drivers/gpu/drm/rockchip/
H A Drockchip_drm_vop2.c1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Author: Andy Yan <andy.yan@rock-chips.com>
12 #include <linux/media-bus-format.h>
44 +----------+ +-------------+ +-----------+
47 +----------+ +-------------+ +---------------+ +-------------+ +-----------+
48 +----------+ +-------------+ |N from 6 layers| | |
49 | Cluster | | Sel 1 from 6| | Overlay0 +--->| Video Port0 | +-----------+
51 +----------+ +-------------+ +---------------+ +-------------+ | LVDS |
52 +----------+ +-------------+ +-----------+
54 | window0 | | Layer2 | +---------------+ +-------------+ +-----------+
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/linux/
H A DMAINTAINERS5 ---------------------------------------------------
7 M: *Mail* patches to: FullName <address@domain>
10 L: *Mailing list* that is relevant to this area
12 Supported: Someone is actually paid to look after this.
14 Odd Fixes: It has a maintainer but they don't have time to do
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
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