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/linux/Documentation/devicetree/bindings/media/
H A Dnxp,imx-mipi-csi2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nxp,imx-mipi-csi2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX7 and i.MX8 MIPI CSI-2 receiver
10 - Rui Miguel Silva <rmfrfs@gmail.com>
11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 description: |-
14 The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2
19 While the CSI-2 receiver is separate from the MIPI D-PHY IP core, the PHY is
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H A Dallwinner,sun6i-a31-mipi-csi2.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/allwinner,sun6i-a31-mipi-csi2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A31 MIPI CSI-2
10 - Paul Kocialkowski <paul.kocialkowski@bootlin.com>
15 - const: allwinner,sun6i-a31-mipi-csi2
16 - items:
17 - const: allwinner,sun8i-v3s-mipi-csi2
18 - const: allwinner,sun6i-a31-mipi-csi2
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H A Drenesas,rzg2l-csi2.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/renesas,rzg2l-csi2.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Renesas RZ/G2L (and alike SoC's) MIPI CSI-2 receiver
11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
14 The CSI-2 receiver device provides MIPI CSI-2 capabilities for the Renesas RZ/G2L
15 (and alike SoCs). MIPI CSI-2 is part of the CRU block which is used in conjunction
21 - enum:
22 - renesas,r9a07g043-csi2 # RZ/G2UL
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H A Dallwinner,sun8i-a83t-mipi-csi2.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/allwinner,sun8i-a83t-mipi-csi2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A83T MIPI CSI-2
10 - Paul Kocialkowski <paul.kocialkowski@bootlin.com>
14 const: allwinner,sun8i-a83t-mipi-csi2
24 - description: Bus Clock
25 - description: Module Clock
26 - description: MIPI-specific Clock
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H A Dnxp,imx8mq-mipi-csi2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nxp,imx8mq-mipi-csi2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MQ MIPI CSI-2 receiver
10 - Martin Kepplinger <martin.kepplinger@puri.sm>
12 description: |-
13 This binding covers the CSI-2 RX PHY and host controller included in the
20 - fsl,imx8mq-mipi-csi2
27 - description: core is the RX Controller Core Clock input. This clock
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H A Dcdns,csi2tx.txt1 Cadence MIPI-CSI2 TX controller
4 The Cadence MIPI-CSI2 TX controller is a CSI-2 bridge supporting up to
8 - compatible: must be set to "cdns,csi2tx" or "cdns,csi2tx-1.3"
9 for version 1.3 of the controller, "cdns,csi2tx-2.1" for v2.1
10 - reg: base address and size of the memory mapped region
11 - clocks: phandles to the clocks driving the controller
12 - clock-names: must contain:
15 * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
19 - phys: phandle to the D-PHY. If it is set, phy-names need to be set
20 - phy-names: must contain "dphy"
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H A Dcdns,csi2rx.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence MIPI-CSI2 RX controller
10 - Maxime Ripard <mripard@kernel.org>
13 The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI
19 - enum:
20 - starfive,jh7110-csi2rx
21 - ti,j721e-csi2rx
22 - const: cdns,csi2rx
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H A Dimx.txt5 ---------------------------
12 - compatible : "fsl,imx-capture-subsystem";
13 - ports : Should contain a list of phandles pointing to camera
18 capture-subsystem {
19 compatible = "fsl,imx-capture-subsystem";
25 --------------
27 This is the device node for the MIPI CSI-2 Receiver core in the i.MX
28 SoC. This is a Synopsys Designware MIPI CSI-2 host controller core
29 combined with a D-PHY core mixed into the same register block. In
30 addition this device consists of an i.MX-specific "CSI2IPU gasket"
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/linux/drivers/media/platform/cadence/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 tristate "Cadence MIPI-CSI2 RX Controller"
14 Support for the Cadence MIPI CSI2 Receiver controller.
17 called cdns-csi2rx.
20 tristate "Cadence MIPI-CSI2 TX Controller"
26 Support for the Cadence MIPI CSI2 Transceiver controller.
29 called cdns-csi2tx.
/linux/Documentation/admin-guide/media/
H A Dimx.rst1 .. SPDX-License-Identifier: GPL-2.0
7 ------------
15 - Image DMA Controller (IDMAC)
16 - Camera Serial Interface (CSI)
17 - Image Converter (IC)
18 - Sensor Multi-FIFO Controller (SMFC)
19 - Image Rotator (IRT)
20 - Video De-Interlacing or Combining Block (VDIC)
26 re-ordering (for example UYVY to YUYV) within the same colorspace, and
27 packed <--> planar conversion. The IDMAC can also perform a simple
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H A Dplatform-cardlist.rst1 .. SPDX-License-Identifier: GPL-2.0
17 am437x-vpfe TI AM437x VPFE
18 aspeed-video Aspeed AST2400 and AST2500
19 atmel-isc ATMEL Image Sensor Controller (ISC)
20 atmel-isi ATMEL Image Sensor Interface (ISI)
24 cdns-csi2rx Cadence MIPI-CSI2 RX Controller
25 cdns-csi2tx Cadence MIPI-CSI2 TX Controller
26 coda-vpu Chips&Media Coda multi-standard codec IP
29 exynos-fimc-is EXYNOS4x12 FIMC-IS (Imaging Subsystem)
30 exynos-fimc-lite EXYNOS FIMC-LITE camera interface
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H A Dipu6-isys.rst1 .. SPDX-License-Identifier: GPL-2.0
9 Copyright |copy| 2023--2024 Intel Corporation
15 Input System (MIPI CSI2 receiver) drivers located under
26 Intel IPU6 is made up of two components - Input System (ISYS) and Processing
29 The Input System mainly works as MIPI CSI-2 receiver which receives and
32 There are 2 driver modules - intel-ipu6 and intel-ipu6-isys. intel-ipu6 is an
34 firmware authentication, DMA mapping and IPU-MMU (internal Memory mapping Unit)
36 sub-device interfaces. The IPU6 ISYS driver supports camera sensors connected
37 to the IPU6 ISYS through V4L2 sub-device sensor drivers.
39 .. Note:: See Documentation/driver-api/media/drivers/ipu6.rst for more
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/linux/Documentation/devicetree/bindings/soc/imx/
H A Dfsl,imx8mp-media-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Elder <paul.elder@ideasonboard.com>
13 The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level peripheral
20 - const: fsl,imx8mp-media-blk-ctrl
21 - const: syscon
26 '#address-cells':
29 '#size-cells':
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/linux/Documentation/userspace-api/media/v4l/
H A Dmetafmt-generic.rst1 .. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
8 Generic line-based metadata formats
14 These generic line-based metadata formats define the memory layout of the data
17 .. _v4l2-meta-fmt-generic-8:
20 -----------------------
22 The V4L2_META_FMT_GENERIC_8 format is a plain 8-bit metadata format. This format
23 is used on CSI-2 for 8 bits per :term:`Data Unit`.
26 packed into one 16-bit Data Unit. Otherwise the 16 bits per pixel dataformat is
27 :ref:`V4L2_META_FMT_GENERIC_CSI2_16 <v4l2-meta-fmt-generic-csi2-16>`.
34 .. flat-table:: Sample 4x2 Metadata Frame
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/linux/Documentation/devicetree/bindings/media/i2c/
H A Dtc358743.txt1 * Toshiba TC358743 HDMI-RX to MIPI CSI2-TX Bridge
3 The Toshiba TC358743 HDMI-RX to MIPI CSI2-TX (H2C) is a bridge that converts
4 a HDMI stream to MIPI CSI-2 TX. It is programmable through I2C.
8 - compatible: value should be "toshiba,tc358743"
9 - clocks, clock-names: should contain a phandle link to the reference clock
14 - reset-gpios: gpio phandle GPIO connected to the reset pin
15 - interrupts: GPIO connected to the interrupt pin
16 - data-lanes: should be <1 2 3 4> for four-lane operation,
17 or <1 2> for two-lane operation
18 - clock-lanes: should be <0>
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/linux/drivers/staging/media/atomisp/include/linux/
H A Datomisp_platform.h1 /* SPDX-License-Identifier: GPL-2.0 */
14 #include <media/v4l2-subdev.h>
60 /* CSI2-MIPI specific format: Generic short packet data. It is used to
73 /* CSI2-MIPI specific format: YUV data.
75 ATOMISP_INPUT_FORMAT_YUV420_8_SHIFT, /* YUV420 8-bit (Chroma Shifted
77 ATOMISP_INPUT_FORMAT_YUV420_10_SHIFT, /* YUV420 8-bit (Chroma Shifted
80 /* CSI2-MIPI specific format: Generic long packet data
82 ATOMISP_INPUT_FORMAT_EMBEDDED, /* Embedded 8-bit non Image Data */
84 /* CSI2-MIPI specific format: User defined byte-based data. For example,
89 ATOMISP_INPUT_FORMAT_USER_DEF1, /* User defined 8-bit data type 1 */
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/linux/Documentation/devicetree/bindings/display/bridge/
H A Drenesas,dsi-csi2-tx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/renesas,dsi-csi2-tx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car MIPI DSI/CSI-2 Encoder
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
13 This binding describes the MIPI DSI/CSI-2 encoder embedded in the Renesas
14 R-Car Gen4 SoCs. The encoder can operate in either DSI or CSI-2 mode, with up
20 - renesas,r8a779a0-dsi-csi2-tx # for V3U
21 - renesas,r8a779g0-dsi-csi2-tx # for V4H
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/linux/drivers/media/platform/samsung/exynos4-is/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
33 module will be called s5p-fimc.
36 tristate "S5P/EXYNOS MIPI-CSI2 receiver (MIPI-CSIS) driver"
41 This is a V4L2 driver for Samsung S5P and EXYNOS4 SoC MIPI-CSI2
42 receiver (MIPI-CSIS) devices.
45 module will be called s5p-csis.
48 tristate "EXYNOS FIMC-LITE camera interface driver"
55 This is a V4L2 driver for Samsung EXYNOS4/5 SoC FIMC-LITE camera
59 module will be called exynos-fimc-lite.
62 tristate "EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver"
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/linux/drivers/media/platform/sunxi/sun6i-mipi-csi2/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0-only
2 sun6i-mipi-csi2-y += sun6i_mipi_csi2.o
4 obj-$(CONFIG_VIDEO_SUN6I_MIPI_CSI2) += sun6i-mipi-csi2.o
/linux/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0-only
2 sun8i-a83t-mipi-csi2-y += sun8i_a83t_mipi_csi2.o sun8i_a83t_dphy.o
4 obj-$(CONFIG_VIDEO_SUN8I_A83T_MIPI_CSI2) += sun8i-a83t-mipi-csi2.o
/linux/drivers/media/platform/sunxi/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 obj-y += sun4i-csi/
4 obj-y += sun6i-csi/
5 obj-y += sun6i-mipi-csi2/
6 obj-y += sun8i-a83t-mipi-csi2/
7 obj-y += sun8i-di/
8 obj-y += sun8i-rotate/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
5 source "drivers/media/platform/sunxi/sun4i-csi/Kconfig"
6 source "drivers/media/platform/sunxi/sun6i-csi/Kconfig"
7 source "drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig"
8 source "drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Kconfig"
9 source "drivers/media/platform/sunxi/sun8i-di/Kconfig"
10 source "drivers/media/platform/sunxi/sun8i-rotate/Kconfig"
/linux/drivers/media/pci/intel/ipu6/
H A Dipu6-isys-csi2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013--2024 Intel Corporation
16 #include <media/media-entity.h>
17 #include <media/v4l2-ctrls.h>
18 #include <media/v4l2-device.h>
19 #include <media/v4l2-event.h>
20 #include <media/v4l2-subdev.h>
22 #include "ipu6-bus.h"
23 #include "ipu6-isys.h"
24 #include "ipu6-isys-csi2.h"
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/linux/Documentation/devicetree/bindings/media/xilinx/
H A Dxlnx,csi2rxss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx MIPI CSI-2 Receiver Subsystem
10 - Vishal Sagar <vishal.sagar@amd.com>
13 The Xilinx MIPI CSI-2 Receiver Subsystem is used to capture MIPI CSI-2
16 The subsystem consists of a MIPI D-PHY in slave mode which captures the
17 data packets. This is passed along the MIPI CSI-2 Rx IP which extracts the
20 For more details, please refer to PG232 Xilinx MIPI CSI-2 Receiver Subsystem.
21 Please note that this bindings includes only the MIPI CSI-2 Rx controller
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/linux/drivers/media/platform/ti/omap3isp/
H A Domap3isp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * TI OMAP3 ISP - Bus Configuration
25 * struct isp_parallel_cfg - Parallel interface configuration
27 * 0 - CAMEXT[13:0] -> CAM[13:0]
28 * 2 - CAMEXT[13:2] -> CAM[11:0]
29 * 4 - CAMEXT[13:4] -> CAM[9:0]
30 * 6 - CAMEXT[13:6] -> CAM[7:0]
32 * 0 - Sample on rising edge, 1 - Sample on falling edge
34 * 0 - Active high, 1 - Active low
36 * 0 - Active high, 1 - Active low
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