xref: /linux/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts (revision fab183d632628381b466a41479489541ac0e29a0) 
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the Ironhide board
4 *
5 * Copyright (C) 2025 Renesas Electronics Corp.
6 */
7
8/dts-v1/;
9#include <dt-bindings/soc/renesas,r8a78000-mfis.h>
10#include "r8a78000.dtsi"
11
12/ {
13	model = "Renesas Ironhide board based on r8a78000";
14	compatible = "renesas,ironhide", "renesas,r8a78000";
15
16	aliases {
17		serial0 = &hscif0;
18	};
19
20	chosen {
21		stdout-path = "serial0:1843200n8";
22	};
23
24	firmware {
25		scmi: scmi {
26			compatible = "arm,scmi";
27			mboxes = <&mfis_scp 2 MFIS_CHANNEL_TX>,
28				 <&mfis_scp 2 MFIS_CHANNEL_RX>;
29			mbox-names = "tx", "rx";
30			shmem = <&scmi_tx_shmem>, <&scmi_rx_shmem>;
31			arm,no-completion-irq;
32			#address-cells = <1>;
33			#size-cells = <0>;
34		};
35	};
36
37	memory@40000000 {
38		device_type = "memory";
39		reg = <0x0 0x40000000 0x0 0x80000000>;
40	};
41
42	memory@1080000000 {
43		device_type = "memory";
44		reg = <0x10 0x80000000 0x0 0x80000000>;
45	};
46
47	memory@1200000000 {
48		device_type = "memory";
49		reg = <0x12 0x00000000 0x1 0x00000000>;
50	};
51
52	memory@1400000000 {
53		device_type = "memory";
54		reg = <0x14 0x00000000 0x1 0x00000000>;
55	};
56
57	memory@1600000000 {
58		device_type = "memory";
59		reg = <0x16 0x00000000 0x1 0x00000000>;
60	};
61
62	memory@1800000000 {
63		device_type = "memory";
64		reg = <0x18 0x00000000 0x1 0x00000000>;
65	};
66
67	memory@1a00000000 {
68		device_type = "memory";
69		reg = <0x1a 0x00000000 0x1 0x00000000>;
70	};
71
72	memory@1c00000000 {
73		device_type = "memory";
74		reg = <0x1c 0x00000000 0x1 0x00000000>;
75	};
76
77	memory@1e00000000 {
78		device_type = "memory";
79		reg = <0x1e 0x00000000 0x1 0x00000000>;
80	};
81
82	reserved-memory {
83		#address-cells = <2>;
84		#size-cells = <2>;
85		ranges;
86
87		/* First 518 MiB is reserved for other purposes. */
88		firmware@40000000 {
89			reg = <0x0 0x40000000 0x0 0x20600000>;
90			no-map;
91		};
92
93		/* Parameters set by IPL. */
94		parameters@8c100000 {
95			reg = <0x0 0x8c100000 0x0 0x00008000>;
96			no-map;
97		};
98
99		/* TFA BL31. */
100		tfa-bl31@8c200000 {
101			reg = <0x0 0x8c200000 0x0 0x00080000>;
102			no-map;
103		};
104
105		/* TEE TZ DRAM. */
106		tee@8c400000 {
107			reg = <0x0 0x8c400000 0x0 0x02000000>;
108			no-map;
109		};
110
111		/* DRAM controller inline ECC areas */
112		ecc@10cccc0000 {
113			reg = <0x10 0xcccc0000 0x0 0x33340000>;
114			no-map;
115		};
116
117		ecc@12cccc0000 {
118			reg = <0x12 0xcccc0000 0x0 0x33340000>;
119			no-map;
120		};
121
122		ecc@14cccc0000 {
123			reg = <0x14 0xcccc0000 0x0 0x33340000>;
124			no-map;
125		};
126
127		ecc@16cccc0000 {
128			reg = <0x16 0xcccc0000 0x0 0x33340000>;
129			no-map;
130		};
131
132		ecc@18cccc0000 {
133			reg = <0x18 0xcccc0000 0x0 0x33340000>;
134			no-map;
135		};
136
137		ecc@1a66660000 {
138			reg = <0x1a 0x66660000 0x0 0x999a0000>;
139			no-map;
140		};
141
142		ecc@1c66660000 {
143			reg = <0x1c 0x66660000 0x0 0x999a0000>;
144			no-map;
145		};
146
147		ecc@1e66660000 {
148			reg = <0x1e 0x66660000 0x0 0x999a0000>;
149			no-map;
150		};
151	};
152};
153
154&extal_clk {
155	clock-frequency = <16666600>;
156};
157
158&extalr_clk {
159	clock-frequency = <32768>;
160};
161
162&hscif0 {
163	uart-has-rtscts;
164	status = "okay";
165};
166
167&mfis_scp {
168	status = "okay";
169};
170
171&scif_clk {
172	clock-frequency = <26000000>;
173};
174
175&stcm_transport {
176	scmi_tx_shmem: sram@1200 {
177		compatible = "arm,scmi-shmem";
178		reg = <0x1200 0x0100>;
179	};
180
181	scmi_rx_shmem: sram@1300 {
182		compatible = "arm,scmi-shmem";
183		reg = <0x1300 0x100>;
184	};
185};
186