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/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dti,j721e-system-controller.yaml95 <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
96 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
97 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
98 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
100 /* SERDES4 lane0/1/2/3 select */
/freebsd/sys/contrib/device-tree/Bindings/soc/ti/
H A Dti,j721e-system-controller.yaml113 <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
114 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
115 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
116 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
118 /* SERDES4 lane0/1/2/3 select */
/freebsd/sys/contrib/device-tree/Bindings/display/bridge/
H A Danalogix,anx7625.yaml45 analogix,lane0-swing:
50 an array of swing register setting for DP tx lane0 PHY.
78 DP TX lane1 swing register setting same with lane0
79 swing, please refer lane0-swing property description.
149 analogix,lane0-swing = /bits/ 8 <0x14 0x54 0x64 0x74>;
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dti,phy-am654-serdes.txt13 1 - PCIe0 Lane0
14 2 - ICSS2 SGMII Lane0
16 0 - PCIe1 Lane0
H A Dphy-rockchip-usbdp.yaml64 3>;", assuming DP lane0 on Type-C phy lane2, DP lane1 on Type-C phy
66 <0, 1, 2, 3>;", assuming DP lane0 on Type-C phy lane0, DP lane1 on Type-C
H A Dairoha,en7581-pcie-phy.yaml22 - description: PCIE lane0 base address
24 - description: PCIE lane0 detection time base address
H A Dqcom,msm8996-qmp-pcie-phy.yaml87 - lane0
H A Dfsl,imx8qm-hsio.yaml55 | | Lane0| Lane1| Lane2|
/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dmediatek-pcie-gen3.yaml86 enum: [ phy, mac, phy-lane0, phy-lane1, phy-lane2 ]
262 - const: phy-lane0
H A Dpci-armada8k.txt25 Must be "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy" for
/freebsd/sys/arm/freescale/imx/
H A Dimx6_ahci.c293 device_printf(dev, "cannot read LANE0 status\n"); in imx6_ahci_attach()
301 device_printf(dev, "time out reading LANE0 status\n"); in imx6_ahci_attach()
/freebsd/sys/contrib/device-tree/src/arm64/airoha/
H A Den7581.dtsi223 reset-names = "phy-lane0", "phy-lane1", "phy-lane2";
266 reset-names = "phy-lane0", "phy-lane1", "phy-lane2";
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-j722s-main.dtsi417 mux-reg-masks = <0x00 0x3>, /* SERDES0 lane0 select */
418 <0x10 0x3>; /* SERDES1 lane0 select */
H A Dk3-j721e-main.dtsi71 mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
72 <0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */
73 <0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */
74 <0x30 0x3>, <0x34 0x3>, /* SERDES3 lane0/1 select */
75 <0x40 0x3>, <0x44 0x3>, /* SERDES4 lane0/1 select */
H A Dk3-j784s4-j742s2-main-common.dtsi82 mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
84 <0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */
86 <0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */
88 <0x40 0x3>, <0x44 0x3>, /* SERDES4 lane0/1 select */
/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt8186-corsola-steelix.dtsi63 analogix,lane0-swing = /bits/ 8 <0x70 0x30>;
H A Dmt8186-corsola-chinchou.dtsi72 analogix,lane0-swing = /bits/ 8 <0x70 0x30>;
/freebsd/sys/contrib/device-tree/src/arm64/rockchip/
H A Drk3588-friendlyelec-cm3588-nas.dts458 /* 1. M.2 socket, CON13: pcie30phy port0 lane0, @fe150000 */
469 /* 3. M.2 socket, CON15: pcie30phy port1 lane0, @fe160000 */
H A Drk3568.dtsi245 /* bifurcation; lane0 when using 1+1 */
/freebsd/sys/contrib/device-tree/src/arm64/marvell/
H A Darmada-8040-mcbin.dtsi188 phy-names = "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy",
H A Darmada-8040-puzzle-m801.dts521 phy-names = "cp1-pcie0-x2-lane0-phy", "cp1-pcie0-x2-lane1-phy";
/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_serdes_25g_regs.h261 /* Lane0 reset signal active low */
H A Dal_hal_pcie_axi_reg.h262 uint32_t lane0; member
272 uint32_t lane0; member
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUAtomicOptimizer.cpp443 Value *Lane0 = B.CreateCall(ReadLane, {V, B.getInt32(0)}); in buildReduction() local
445 return buildNonAtomicBinOp(B, Op, Lane0, Lane32); in buildReduction()
/illumos-gate/usr/src/uts/common/io/hxge/
H A Dhxge_peu_hw.h1807 * multiplied by 16. lane0 is bits[15:0], lane1 is bits[31:16],
1815 * lane0 is bits[15:0], which is gbtDebug0[15:0] lane1 is
2008 * PIPE. The pipeDebug[0:15] bus is provided for each lane. lane0
2016 * lane0 is bit[15:0], which is pipeDebug0[15:0] lane1 is
2065 * PIPE. The pipeDebug[0:15] bus is provided for each lane. lane0
2119 * PIPE. The pipeDebug[0:15] bus is provided for each lane. lane0
2176 * PIPE. The pipeDebug[0:15] bus is provided for each lane. lane0

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