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/linux/drivers/phy/marvell/
H A Dphy-mvebu-cp110-comphy.c129 * A lane is described by the following bitfields:
182 unsigned lane; member
190 .lane = _lane, \
200 .lane = _lane, \
209 /* lane 0 */
214 /* lane 1 */
221 /* lane 2 */
230 /* lane 3 */
237 /* lane 4 */
250 /* lane
277 mvebu_comphy_smc(unsigned long function,unsigned long phys,unsigned long lane,unsigned long mode) mvebu_comphy_smc() argument
295 mvebu_comphy_get_mode(bool fw_mode,int lane,int port,enum phy_mode mode,int submode) mvebu_comphy_get_mode() argument
325 mvebu_comphy_get_mux(int lane,int port,enum phy_mode mode,int submode) mvebu_comphy_get_mux() argument
331 mvebu_comphy_get_fw_mode(int lane,int port,enum phy_mode mode,int submode) mvebu_comphy_get_fw_mode() argument
337 mvebu_comphy_ethernet_init_reset(struct mvebu_comphy_lane * lane) mvebu_comphy_ethernet_init_reset() argument
453 mvebu_comphy_init_plls(struct mvebu_comphy_lane * lane) mvebu_comphy_init_plls() argument
496 struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); mvebu_comphy_set_mode_sgmii() local
529 struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); mvebu_comphy_set_mode_rxaui() local
582 struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); mvebu_comphy_set_mode_10gbaser() local
724 struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); mvebu_comphy_power_on_legacy() local
768 struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); mvebu_comphy_power_on() local
856 struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); mvebu_comphy_set_mode() local
876 struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); mvebu_comphy_power_off_legacy() local
899 struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); mvebu_comphy_power_off() local
922 struct mvebu_comphy_lane *lane; mvebu_comphy_xlate() local
1037 struct mvebu_comphy_lane *lane; mvebu_comphy_probe() local
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H A Dphy-mvebu-a3700-comphy.c40 * When accessing common PHY lane registers directly, we need to shift by 1,
175 * This register is not from PHY lane register space. It only exists in the
176 * indirect register space, before the actual PHY lane 2 registers. So the
184 #define COMPHY_PHY_REG(lane, reg) (((1 - (lane)) * 0x28) + ((reg) & 0x3f)) argument
227 unsigned int lane; member
234 .lane = _lane, \
246 /* lane 0 */
251 /* lane 1 */
256 /* lane 2 */
387 /* Used for accessing lane 2 registers (SATA/USB3 PHY) */
[all …]
H A Dphy-armada38x-comphy.c47 struct a38x_comphy_lane lane[MAX_A38X_COMPHY]; member
52 * row index = serdes lane,
64 static void a38x_set_conf(struct a38x_comphy_lane *lane, bool enable) in a38x_set_conf() argument
66 struct a38x_comphy *priv = lane->priv; in a38x_set_conf()
72 conf |= BIT(lane->port); in a38x_set_conf()
74 conf &= ~BIT(lane->port); in a38x_set_conf()
79 static void a38x_comphy_set_reg(struct a38x_comphy_lane *lane, in a38x_comphy_set_reg() argument
84 val = readl_relaxed(lane->base + offset) & ~mask; in a38x_comphy_set_reg()
85 writel(val | value, lane->base + offset); in a38x_comphy_set_reg()
88 static void a38x_comphy_set_speed(struct a38x_comphy_lane *lane, in a38x_comphy_set_speed() argument
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/linux/drivers/phy/freescale/
H A Dphy-fsl-imx8qm-hsio.c96 struct imx_hsio_lane lane[MAX_NUM_LANE]; member
119 struct imx_hsio_lane *lane = phy_get_drvdata(phy); in imx_hsio_init() local
120 struct imx_hsio_priv *priv = lane->priv; in imx_hsio_init()
124 switch (lane->phy_type) { in imx_hsio_init()
126 lane->phy_mode = PHY_MODE_PCIE; in imx_hsio_init()
127 if (lane->ctrl_index == 0) { /* PCIEA */ in imx_hsio_init()
128 lane->ctrl_off = 0; in imx_hsio_init()
129 lane->phy_off = 0; in imx_hsio_init()
132 if (lane->idx == 0) in imx_hsio_init()
133 lane->clks[i].id = lan0_pcie_clks[i]; in imx_hsio_init()
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/linux/drivers/gpu/drm/amd/display/dc/link/protocols/
H A Dlink_dp_training.c305 uint32_t lane; in maximize_lane_settings() local
313 for (lane = 1; lane < lt_settings->link_settings.lane_count; lane++) { in maximize_lane_settings()
314 if (lane_settings[lane].VOLTAGE_SWING > max_requested.VOLTAGE_SWING) in maximize_lane_settings()
315 max_requested.VOLTAGE_SWING = lane_settings[lane].VOLTAGE_SWING; in maximize_lane_settings()
317 if (lane_settings[lane].PRE_EMPHASIS > max_requested.PRE_EMPHASIS) in maximize_lane_settings()
318 max_requested.PRE_EMPHASIS = lane_settings[lane].PRE_EMPHASIS; in maximize_lane_settings()
319 if (lane_settings[lane].FFE_PRESET.settings.level > in maximize_lane_settings()
322 lane_settings[lane].FFE_PRESET.settings.level; in maximize_lane_settings()
347 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in maximize_lane_settings()
348 lane_settings[lane].VOLTAGE_SWING = max_requested.VOLTAGE_SWING; in maximize_lane_settings()
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/linux/drivers/gpu/drm/i915/display/
H A Dvlv_dpio_phy_regs.h19 #define _VLV_TX(ch, lane, dw) (0x80 + (ch) * 0x2400 + (lane) * 0x200 + (dw) * 4) argument
156 #define VLV_TX_DW2(ch, lane) _VLV_TX((ch), (lane), 2) argument
163 #define VLV_TX_DW3(ch, lane) _VLV_TX((ch), (lane), 3) argument
170 #define VLV_TX_DW4(ch, lane) _VLV_TX((ch), (lane), 4) argument
177 #define VLV_TX_DW5(ch, lane) _VLV_TX((ch), (lane), 5) argument
181 #define VLV_TX_DW11(ch, lane) _VLV_TX((ch), (lane), 11) argument
184 #define VLV_TX_DW14(ch, lane) _VLV_TX((ch), (lane), 14) argument
290 #define CHV_TX_DW0(ch, lane) _VLV_TX((ch), (lane), 0) argument
291 #define CHV_TX_DW1(ch, lane) _VLV_TX((ch), (lane), 1) argument
292 #define CHV_TX_DW2(ch, lane) _VLV_TX((ch), (lane), 2) argument
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H A Dintel_cx0_phy_regs.h39 #define _XELPDP_PORT_M2P_MSGBUS_CTL(idx, lane) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \ argument
43 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4)
44 #define XELPDP_PORT_M2P_MSGBUS_CTL(i915__, port, lane) \ argument
46 _XELPDP_PORT_M2P_MSGBUS_CTL(__xe2lpd_port_idx(port), lane) : \
47 _XELPDP_PORT_M2P_MSGBUS_CTL(port, lane))
59 #define _XELPDP_PORT_P2M_MSGBUS_STATUS(idx, lane) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \ argument
63 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4 + 8)
64 #define XELPDP_PORT_P2M_MSGBUS_STATUS(i915__, port, lane) \ argument
66 _XELPDP_PORT_P2M_MSGBUS_STATUS(__xe2lpd_port_idx(port), lane) : \
67 _XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane))
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H A Dbxt_dpio_phy_regs.h28 #define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \ argument
29 ((lane) & 1) * 0x80)
30 #define _MMIO_BXT_PHY_CH_LN(phy, ch, lane, reg_ch0, reg_ch1) \ argument
31 _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) + _BXT_LANE_OFFSET(lane))
101 /* BXT PHY common lane registers */
209 #define BXT_PORT_TX_DW2_LN(phy, ch, lane) _MMIO_BXT_PHY_CH_LN(phy, ch, lane, \ argument
226 #define BXT_PORT_TX_DW3_LN(phy, ch, lane) _MMIO_BXT_PHY_CH_LN(phy, ch, lane, \ argument
241 #define BXT_PORT_TX_DW4_LN(phy, ch, lane) _MMIO_BXT_PHY_CH_LN(phy, ch, lane, \ argument
256 #define BXT_PORT_TX_DW5_LN(phy, ch, lane) _MMIO_BXT_PHY_CH_LN(phy, ch, lane, \ argument
269 #define BXT_PORT_TX_DW14_LN(phy, ch, lane) _MMIO_BXT_PHY_CH_LN(phy, ch, lane, \ argument
H A Dintel_dpio_phy.c49 * houses a common lane part which contains the PLL and other common
50 * logic. CH0 common lane also contains the IOSF-SB logic for the
65 * Additionally the PHY also contains an AUX lane with AUX blocks
71 * Generally on VLV/CHV the common lane corresponds to the pipe and
278 * Like intel_de_rmw() but reads from a single per-lane register and
302 int lane, n_entries; in bxt_dpio_phy_set_signal_levels() local
312 * can read only lane registers and we pick lanes 0/1 for that. in bxt_dpio_phy_set_signal_levels()
318 for (lane = 0; lane < crtc_state->lane_count; lane++) { in bxt_dpio_phy_set_signal_levels()
319 int level = intel_ddi_level(encoder, crtc_state, lane); in bxt_dpio_phy_set_signal_levels()
321 intel_de_rmw(display, BXT_PORT_TX_DW2_LN(phy, ch, lane), in bxt_dpio_phy_set_signal_levels()
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H A Dintel_dp_link_training.c185 * still taking into account any LTTPR common lane- rate/count limits. in intel_dp_init_lttpr_phys()
403 int lane) in intel_dp_get_lane_adjust_tx_ffe_preset() argument
408 lane = min(lane, crtc_state->lane_count - 1); in intel_dp_get_lane_adjust_tx_ffe_preset()
409 tx_ffe = drm_dp_get_adjust_tx_ffe_preset(link_status, lane); in intel_dp_get_lane_adjust_tx_ffe_preset()
411 for (lane = 0; lane < crtc_state->lane_count; lane++) in intel_dp_get_lane_adjust_tx_ffe_preset()
412 tx_ffe = max(tx_ffe, drm_dp_get_adjust_tx_ffe_preset(link_status, lane)); in intel_dp_get_lane_adjust_tx_ffe_preset()
423 int lane) in intel_dp_get_lane_adjust_vswing_preemph() argument
431 lane = min(lane, crtc_state->lane_count - 1); in intel_dp_get_lane_adjust_vswing_preemph()
433 v = drm_dp_get_adjust_request_voltage(link_status, lane); in intel_dp_get_lane_adjust_vswing_preemph()
434 p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); in intel_dp_get_lane_adjust_vswing_preemph()
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/linux/drivers/platform/x86/intel/pmc/
H A Dspt.c22 {"MPHY CORE LANE 0", SPT_PMC_BIT_MPHY_LANE0},
23 {"MPHY CORE LANE 1", SPT_PMC_BIT_MPHY_LANE1},
24 {"MPHY CORE LANE 2", SPT_PMC_BIT_MPHY_LANE2},
25 {"MPHY CORE LANE 3", SPT_PMC_BIT_MPHY_LANE3},
26 {"MPHY CORE LANE 4", SPT_PMC_BIT_MPHY_LANE4},
27 {"MPHY CORE LANE 5", SPT_PMC_BIT_MPHY_LANE5},
28 {"MPHY CORE LANE 6", SPT_PMC_BIT_MPHY_LANE6},
29 {"MPHY CORE LANE 7", SPT_PMC_BIT_MPHY_LANE7},
30 {"MPHY CORE LANE 8", SPT_PMC_BIT_MPHY_LANE8},
31 {"MPHY CORE LANE 9", SPT_PMC_BIT_MPHY_LANE9},
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/linux/drivers/phy/tegra/
H A Dxusb-tegra124.c292 struct tegra_xusb_lane *lane; in tegra124_usb3_save_context() local
300 lane = port->base.lane; in tegra124_usb3_save_context()
302 if (lane->pad == padctl->pcie) in tegra124_usb3_save_context()
303 offset = XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL6(lane->index); in tegra124_usb3_save_context()
452 static void tegra124_usb2_lane_remove(struct tegra_xusb_lane *lane) in tegra124_usb2_lane_remove() argument
454 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane); in tegra124_usb2_lane_remove()
466 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra124_usb2_phy_init() local
468 return tegra124_xusb_padctl_enable(lane->pad->padctl); in tegra124_usb2_phy_init()
473 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra124_usb2_phy_exit() local
475 return tegra124_xusb_padctl_disable(lane->pad->padctl); in tegra124_usb2_phy_exit()
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H A Dxusb-tegra210.c447 static int tegra210_usb3_lane_map(struct tegra_xusb_lane *lane) in tegra210_usb3_lane_map() argument
452 if (map->index == lane->index && in tegra210_usb3_lane_map()
453 strcmp(map->type, lane->pad->soc->name) == 0) { in tegra210_usb3_lane_map()
454 dev_dbg(lane->pad->padctl->dev, "lane = %s map to port = usb3-%d\n", in tegra210_usb3_lane_map()
455 lane->pad->soc->lanes[lane->index].name, map->port); in tegra210_usb3_lane_map()
706 struct tegra_xusb_lane *lane = tegra_xusb_find_lane(padctl, "sata", 0); in tegra210_sata_uphy_enable() local
716 if (IS_ERR(lane)) in tegra210_sata_uphy_enable()
722 usb = tegra_xusb_lane_check(lane, "usb3-ss"); in tegra210_sata_uphy_enable()
1058 static int tegra210_usb3_enable_phy_sleepwalk(struct tegra_xusb_lane *lane, in tegra210_usb3_enable_phy_sleepwalk() argument
1061 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_usb3_enable_phy_sleepwalk()
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H A Dxusb.h55 int tegra_xusb_lane_parse_dt(struct tegra_xusb_lane *lane,
63 to_usb3_lane(struct tegra_xusb_lane *lane) in to_usb3_lane() argument
65 return container_of(lane, struct tegra_xusb_usb3_lane, base); in to_usb3_lane()
76 to_usb2_lane(struct tegra_xusb_lane *lane) in to_usb2_lane() argument
78 return container_of(lane, struct tegra_xusb_usb2_lane, base); in to_usb2_lane()
86 to_ulpi_lane(struct tegra_xusb_lane *lane) in to_ulpi_lane() argument
88 return container_of(lane, struct tegra_xusb_ulpi_lane, base); in to_ulpi_lane()
105 to_hsic_lane(struct tegra_xusb_lane *lane) in to_hsic_lane() argument
107 return container_of(lane, struct tegra_xusb_hsic_lane, base); in to_hsic_lane()
115 to_pcie_lane(struct tegra_xusb_lane *lane) in to_pcie_lane() argument
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H A Dxusb-tegra186.c321 static void tegra186_usb2_lane_remove(struct tegra_xusb_lane *lane) in tegra186_usb2_lane_remove() argument
323 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane); in tegra186_usb2_lane_remove()
328 static int tegra186_utmi_enable_phy_sleepwalk(struct tegra_xusb_lane *lane, in tegra186_utmi_enable_phy_sleepwalk() argument
331 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra186_utmi_enable_phy_sleepwalk()
333 unsigned int index = lane->index; in tegra186_utmi_enable_phy_sleepwalk()
477 static int tegra186_utmi_disable_phy_sleepwalk(struct tegra_xusb_lane *lane) in tegra186_utmi_disable_phy_sleepwalk() argument
479 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra186_utmi_disable_phy_sleepwalk()
481 unsigned int index = lane->index; in tegra186_utmi_disable_phy_sleepwalk()
525 static int tegra186_utmi_enable_phy_wake(struct tegra_xusb_lane *lane) in tegra186_utmi_enable_phy_wake() argument
527 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra186_utmi_enable_phy_wake()
[all …]
/linux/drivers/phy/
H A Dphy-xgene.c268 /* PHY lane CSR accessing from SDS indirectly */
520 u32 speed[MAX_LANE]; /* Index for override parameter per lane */
658 static void serdes_wr(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 data) in serdes_wr() argument
664 reg += lane * SERDES_LANE_STRIDE; in serdes_wr()
673 static void serdes_rd(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 *data) in serdes_rd() argument
678 reg += lane * SERDES_LANE_STRIDE; in serdes_rd()
684 static void serdes_clrbits(struct xgene_phy_ctx *ctx, int lane, u32 reg, in serdes_clrbits() argument
689 serdes_rd(ctx, lane, reg, &val); in serdes_clrbits()
691 serdes_wr(ctx, lane, reg, val); in serdes_clrbits()
694 static void serdes_setbits(struct xgene_phy_ctx *ctx, int lane, u32 reg, in serdes_setbits() argument
[all …]
/linux/Documentation/devicetree/bindings/usb/
H A Donnn,nb7vpq904m.yaml48 An array of physical data lane indexes. Position determines how
51 Lane number represents the following
52 - 0 is RX2 lane
53 - 1 is TX2 lane
54 - 2 is TX1 lane
55 - 3 is RX1 lane
66 - Port A to RX2 lane
67 - Port B to TX2 lane
68 - Port C to TX1 lane
69 - Port D to RX1 lane
[all …]
/linux/sound/soc/tegra/
H A Dtegra186_asrc.c109 if (asrc->lane[id].ratio_source != in tegra186_asrc_runtime_resume()
116 asrc->lane[id].int_part); in tegra186_asrc_runtime_resume()
121 asrc->lane[id].frac_part); in tegra186_asrc_runtime_resume()
173 asrc->lane[id].input_thresh); in tegra186_asrc_in_hw_params()
196 asrc->lane[id].output_thresh); in tegra186_asrc_out_hw_params()
206 if (asrc->lane[id].hwcomp_disable) { in tegra186_asrc_out_hw_params()
225 1, asrc->lane[id].ratio_source); in tegra186_asrc_out_hw_params()
227 if (asrc->lane[id].ratio_source == TEGRA186_ASRC_RATIO_SOURCE_SW) { in tegra186_asrc_out_hw_params()
230 asrc->lane[id].int_part); in tegra186_asrc_out_hw_params()
233 asrc->lane[id].frac_part); in tegra186_asrc_out_hw_params()
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/linux/Documentation/devicetree/bindings/media/i2c/
H A Dst,st-mipid02.yaml17 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2
18 second input port is a single lane 800Mbps. Both ports support clock
19 and data lane polarity swap. First port also supports data lane swap.
65 Single-lane operation shall be <1> or <2> .
66 Dual-lane operation shall be <1 2> or <2 1> .
70 lane-polarities:
72 Any lane can be inverted or not.
91 Single-lane operation shall be <1> or <2> .
94 lane-polarities:
96 Any lane can be inverted or not.
/linux/drivers/thunderbolt/
H A Dlc.c97 u32 ctrl, lane; in tb_lc_set_port_configured() local
111 /* Resolve correct lane */ in tb_lc_set_port_configured()
113 lane = TB_LC_SX_CTRL_L1C; in tb_lc_set_port_configured()
115 lane = TB_LC_SX_CTRL_L2C; in tb_lc_set_port_configured()
118 ctrl |= lane; in tb_lc_set_port_configured()
122 ctrl &= ~lane; in tb_lc_set_port_configured()
155 u32 ctrl, lane; in tb_lc_set_xdomain_configured() local
169 /* Resolve correct lane */ in tb_lc_set_xdomain_configured()
171 lane = TB_LC_SX_CTRL_L1D; in tb_lc_set_xdomain_configured()
173 lane = TB_LC_SX_CTRL_L2D; in tb_lc_set_xdomain_configured()
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/linux/drivers/gpu/drm/bridge/analogix/
H A Danalogix_dp_core.c229 int lane, lane_count, retval; in analogix_dp_link_start() local
236 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
237 dp->link_train.cr_loop[lane] = 0; in analogix_dp_link_start()
267 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
268 dp->link_train.training_lane[lane] = in analogix_dp_link_start()
283 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
284 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 | in analogix_dp_link_start()
295 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane) in analogix_dp_get_lane_status() argument
297 int shift = (lane & 1) * 4; in analogix_dp_get_lane_status()
298 u8 link_value = link_status[lane >> 1]; in analogix_dp_get_lane_status()
[all …]
/linux/drivers/phy/mediatek/
H A Dphy-mtk-pcie.c36 * struct mtk_pcie_lane_efuse - eFuse data for each lane
40 * @lane_efuse_supported: software eFuse data is supported for this lane
51 * @num_lanes: supported lane numbers
67 * @efuse: pointer to eFuse data for each lane
81 unsigned int lane) in mtk_pcie_efuse_set_lane() argument
83 struct mtk_pcie_lane_efuse *data = &pcie_phy->efuse[lane]; in mtk_pcie_efuse_set_lane()
90 lane * PEXTP_ANA_LANE_OFFSET; in mtk_pcie_efuse_set_lane()
134 unsigned int lane) in mtk_pcie_efuse_read_for_lane() argument
136 struct mtk_pcie_lane_efuse *efuse = &pcie_phy->efuse[lane]; in mtk_pcie_efuse_read_for_lane()
141 snprintf(efuse_id, sizeof(efuse_id), "tx_ln%d_pmos", lane); in mtk_pcie_efuse_read_for_lane()
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/linux/include/linux/phy/
H A Dphy-mipi-dphy.h20 * Clock transitions and disable the Clock Lane HS-RX.
30 * send HS clock after the last associated Data Lane has
42 * the transmitter prior to any associated Data Lane beginning
53 * Lane LP-00 Line state immediately before the HS-0 Line
65 * should ignore any Clock Lane HS transitions, starting from
76 * Time, in picoseconds, for the Clock Lane receiver to enable
105 * Time, in picoseconds, for the Data Lane receiver to enable
137 * Lane LP-00 Line state immediately before the HS-0 Line
149 * shall ignore any Data Lane HS transitions, starting from
161 * should ignore any transitions on the Data Lane, following a
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/linux/drivers/media/platform/ti/omap3isp/
H A Domap3isp.h26 * @data_lane_shift: Data lane shifter
64 * struct isp_csiphy_lane: CCP2/CSI2 lane position and polarity
65 * @pos: position of the lane
66 * @pol: polarity of the lane
77 * struct isp_csiphy_lanes_cfg - CCP2/CSI2 lane configuration
79 * @clk: Clock lane configuration
99 * @lanecfg: CCP2/CSI2 lane configuration
114 * @lanecfg: CSI-2 lane configuration
/linux/drivers/net/ethernet/ti/
H A Dnetcp_xgbepcsr.c146 /* lane is 0 based */
148 void __iomem *serdes_regs, int lane) in netcp_xgbe_serdes_lane_config() argument
152 /* lane setup */ in netcp_xgbe_serdes_lane_config()
156 (0x200 * lane), in netcp_xgbe_serdes_lane_config()
162 reg_rmw(serdes_regs + (0x200 * lane) + 0x0380, in netcp_xgbe_serdes_lane_config()
166 reg_rmw(serdes_regs + (0x200 * lane) + 0x03c0, in netcp_xgbe_serdes_lane_config()
182 void __iomem *serdes_regs, int lane) in netcp_xgbe_serdes_lane_enable() argument
184 /* Set Lane Control Rate */ in netcp_xgbe_serdes_lane_enable()
185 writel(0xe0e9e038, serdes_regs + 0x1fe0 + (4 * lane)); in netcp_xgbe_serdes_lane_enable()
258 /* For 2 lane Phy-B, lane0 is actually lane1 */ in netcp_xgbe_serdes_write_tbus_addr()
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