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/freebsd/sys/crypto/ccp/
H A Dccp_lsb.c64 * Look for a private LSB for each queue. There are 7 general purpose LSBs
66 * queues' access to some LSBs; we hope it is fairly sane and just use a dumb
67 * greedy algorithm to assign LSBs to queues.
H A Dccp.h113 unsigned lsb_mask; /* LSBs available to queue */
/freebsd/sys/contrib/device-tree/Bindings/gpio/
H A Dgpio-stp-xway.txt6 to drive the 2 LSBs of the cascade automatically.
22 - lantiq,dsl : The dsl core can control the 2 LSBs of the gpio cascade. This 2 bit
H A Dgpio-stp-xway.yaml54 The dsl core can control the 2 LSBs of the gpio cascade. This 2 bit
/freebsd/contrib/llvm-project/llvm/lib/Transforms/AggressiveInstCombine/
H A DAggressiveInstCombineInternal.h68 /// Number of LSBs that are needed to generate a valid expression.
70 /// Minimum number of LSBs needed to generate the ValidBitWidth.
/freebsd/sys/contrib/vchiq/interface/vchiq_arm/
H A Dvchiq_pagelist.h48 unsigned long addrs[1]; /* N.B. 12 LSBs hold the number of following
/freebsd/sys/contrib/device-tree/Bindings/iio/dac/
H A Dad5755.txt79 Valid values for the step size LSBs:
/freebsd/sys/dev/dpaa2/
H A Ddpaa2_ni.h428 uint8_t efh_type; /* EFH type is in the 4 LSBs. */
436 uint8_t extract_type; /* Extraction type is in the 4 LSBs */
/freebsd/sys/dev/ath/ath_hal/ar5210/
H A Dar5210_keycache.c84 * the 4 MSBs, and MacHi is the 2 LSBs. in ar5210SetKeyCacheEntryMac()
/freebsd/sys/dev/ath/ath_hal/ar5211/
H A Dar5211_keycache.c93 * the 4 MSBs, and MacHi is the 2 LSBs. in ar5211SetKeyCacheEntryMac()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMatInt.cpp122 // Reduce the shift amount and add zeros to the LSBs so it will match in generateInstSeqImpl()
128 // Reduce the shift amount and add zeros to the LSBs so it will match in generateInstSeqImpl()
/freebsd/crypto/openssl/include/crypto/
H A Dmd32_common.h240 * with eventual overflows as we *save* only 32 LSBs in
/freebsd/share/man/man3/
H A Dqmath.3232 .Pq LSBs
/freebsd/sys/contrib/dev/athk/ath11k/
H A Ddp.h1464 * | cookie LSBs |
1512 * Value: LSBs of the opaque cookie specified by the host-side requestor
1599 * | cookie LSBs |
1618 * Value: LSBs of the opaque cookie specified by the host-side requestor
/freebsd/sys/contrib/dpdk_rte_lpm/
H A Drte_common.h401 * The integer whose MSBs need to be combined with its LSBs
423 * The integer whose MSBs need to be combined with its LSBs
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVPrepareFunctions.cpp326 // We want the "rotate" number of the more significant int's LSBs (MSBs) to in lowerFunnelShifts()
332 // the LSBs. in lowerFunnelShifts()
/freebsd/sys/dev/ath/ath_hal/ar5212/
H A Dar5212_keycache.c122 * the 4 MSBs, and MacHi is the 2 LSBs. in ar5212SetKeyCacheEntryMac()
/freebsd/sys/sys/
H A Dqmath.h32 * The 3 LSBs of all base data types are reserved for embedded control data:
73 /* Number of LSBs reserved for control data. */
/freebsd/contrib/llvm-project/compiler-rt/lib/builtins/hexagon/
H A Ddfmul.S212 // * Check the LSBs for inexact; if inexact also set underflow
H A Ddfdiv.S245 #define FUDGE2 4 // how many guard/round to keep at lsbs
/freebsd/sys/dev/mii/
H A Dmiidevs101 /* bad byteorder (bits "q" and "r" (= LSBs byte 3) lost) */
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_keycache.c154 * the 4 MSBs, and mac_hi is the 2 LSBs. in ar9300_set_key_cache_entry_mac()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZb.td685 // Match a shifted 0xffffffff mask. Use SRLI to clear the LSBs and SLLI_UW to
723 // Use SRLI to clear the LSBs and SHXADD_UW to mask and shift.
/freebsd/sys/contrib/dev/athk/ath12k/
H A Ddp.h1664 * | cookie LSBs |
1712 * Value: LSBs of the opaque cookie specified by the host-side requestor
/freebsd/sys/contrib/dev/athk/ath10k/
H A Dhtt.h814 u8 seq_num_start; /* it is 6 LSBs of 802.11 seq no */
815 u8 seq_num_end; /* it is 6 LSBs of 802.11 seq no */

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